Experimental Validation of a Faithful Binary Circuit Model

Abstract

Fast digital timing simulations based on continuous-time, digital-value circuit models are an attractive and heavily used alternative to analog simulations. Models based on analytic delay formulas are particularly interesting here, as they also facilitate formal verification and delay bound synthesis of complex circuits. Recently, Függer et al. (arXiv:1406.2544) proposed a circuit model based on so-called involution channels. It is the first binary circuit model that realistically captures solvability of short-pulse filtration, a non-trivial glitch propagation problem related to building one-shot inertial delays.In this work, we address the question of whether involution channels also accurately model the delay of real circuits. Using both Spice simulations and physical measurements, we confirm that modeling an inverter chain by involution channels accurately describes reality. We also demonstrate that transitions in vanishing pulse trains are accurately predicted by the involution model. For our Spice simulations, we used both UMC-90 and UMC-65 technology, with varying supply voltages from nominal down to near sub-threshold range. The measurements were performed on a specialpurpose UMC-90 ASIC that combines an inverter chain with low-intrusive high-speed on-chip analog amplifiers.

A faithful binary circuit model with adversarial noise

“…In this section, we complement the proof of faithfulness provided in the previous section with simulation experiments and measurement results, which confirm that our η-involution model indeed captures reality better than the original involution model [12]. Whereas more experiments, with different technologies and more complex circuits (including multi-input gates), would be needed to actually claim improved model coverage, our results are nevertheless encouraging.…”

“…We employ the same experimental setup as in [12], which uses UMC-90 nm and UMC-65 nm bulk CMOS 7-stage inverter chains as the primary targets. For UMC-65, we resorted to Spice simulations of a standard cell library implementation, for UMC-90, we relied on a custom ASIC [8].…”

“…For convenience, we provide the delay functions determined in [12] in Fig. 7 (δ ↓ for UMC-90, measurements).…”

“…Consequently, the involution model is also faithful for one-shot latches. Moreover, in [12], Najvirt et al used both measurements and Spice simulations to show that the involution model can also be made reasonably accurate by suitable parametrization, in the sense that it nicely (though not perfectly) predicts the actual glitch propagation behavior of a real circuit, namely, an inverter chain.…”

The Involution Tool for Accurate Digital Timingand Power Analysis

“…Types of the IM differ in the instance of delay functions they use. In [11], the authors utilized both SPICE simulations and real measurements to demonstrate that the involution model predicts the behavior of a real circuit, namely, an inverter chain, reasonably accurate.…”