Pt Gate Sink-In Process Details Impact on InP HEMT DC and RF Performance

Saranovac, Tamara; Hambitzer, Anna; Ruiz, Diego Calvo; Ostinelli, O.; Bolognesi, C.R.

doi:10.1109/tsm.2017.2749479

Cited by 15 publications

(4 citation statements)

References 14 publications

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“…[18] Besides, the smaller d of device A caused by "Pt sinking" can also increase the V th and g m max . [19][20][21][22] Therefore, the formation of Pt distribution in Schottky contact metal can be explained as being due to the middle metal layer Pt spreading into the gate recess during the gate metal evaporation, which not only expands the gate length but also increases the Ti-based Schottky barrier height. The differences in V th and g m max between device A and device B are exactly caused by the differences in Pt distribution.…”

Section: Characteristicsmentioning

confidence: 99%

Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs*

Tong

Ding

et al. 2021

Chinese Phys. B

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The T-gate stem height of InAlAs/InGaAs InP-based high electron mobility transistor (HEMT) is increased from 165 nm to 250 nm. The influences of increasing the gate stem height on the direct current (DC) and radio frequency (RF) performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage (V th) of 60 mV than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length, which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the InGaAs channel so that the transconductance (g m) of the high gate stem device is 70 mS/mm larger than that of the short stem device. As for the RF performances, the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum f t of 270 GHz and f max of 460 GHz, while the short gate stem device has a maximum f t of 240 GHz and the f max of 370 GHz.

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Section: Characteristicsmentioning

confidence: 99%

Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs*

Tong

Ding

et al. 2021

Chinese Phys. B

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“…The Tgate electrode was formed with two separate exposures of a multilayer photoresist stack to define the gate foot and head separately and deposition of a Pt/Ti/Pt/Au metal stack. The gates were sunk nm through the InP etch-stop and into the AlInAs barrier at 250 • C as per [10] and passivated with a 15-nm Al 2 O 3 layer by atomic layer deposition (ALD). Careful measurements using focused ion-beam (FIB) cross sections on all structures confirmed a 50-nm gate footprint, as shown in Fig.…”

Section: Device Fabricationmentioning

confidence: 99%

“…InAs insets in indium-rich GaInAs channels evolved toward larger conduction band offsets and better carrier confinement [6]. Combined refinements in low-parasitics process architectures and layer epitaxy enabled record transconductances and short-circuited current-gain cutoff frequencies ( f T ) [7]- [9], as the two quantities are linked according to the following equation [10]:…”

Section: Introductionmentioning

confidence: 99%

InAs Channel Inset Effects on the DC, RF, and Noise Properties of InP pHEMTs

Ruiz

Saranovac

Han

et al. 2019

IEEE Trans. Electron Devices

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GaInAs/InAs composite channels in InP-based pHEMTs enable wideband and/or low-noise performances because of their superior carrier transport properties. To date, the influence of the InAs inset design details on transistor performance has not been parametrized in the literature. We present a systematic study of the effects of the InAs channel inset thickness on transistor characteristics and cutoff frequencies versus temperature, and on the noise performance at 300 K. The epitaxial layer structures considered here incorporate 2 to 5-nm InAs insets in a fixed total composite channel thickness. All layers exhibit excellent electron mobilities (from 40 200 to 54 800 cm 2 /Vs at 77 K). Thicker InAs insets improve both the current gain cutoff frequency (f T) and the maximum oscillation frequency (f MAX). However, they also result in higher gate leakage currents and increased channel impact ionization. 50-nm gate length pHEMTs with a 5-nm InAs inset feature the highest simultaneous f T /f MAX ≥ 390/675 (455/800) GHz at 300 (15) K for a low-noise bias but exhibit the poorest minimum noise figure NF MIN. Whereas higher f T (and/or f MAX) values have traditionally been associated with improved noise performances, this is no longer the case.

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“…Low noise microwave amplifiers based on high electron mobility transistors (HEMTs) are widely used in scientific applications ranging from radio astronomy [1] to quantum computing [2,3]. Decades of progress in device fabrication have yielded significant advances in figures of merit such as transconductance [4][5][6], gain [7], unity gain cutoff frequency [8][9][10], maximum oscillation frequency [11], and power consumption [12,13]. The resulting devices exhibit excellent noise performance, with minimum reported noise figures of HEMTs around a factor of 5 above the standard quantum limit in the 1-100 GHz frequency range [7,9,14,15].…”

Section: Introductionmentioning

confidence: 99%

Theory of drain noise in high electron mobility transistors based on real-space transfer

Esho

Choi

Minnich

2022

Journal of Applied Physics

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High electron mobility transistors are widely used as microwave amplifiers owing to their low microwave noise figure. Electronic noise in these devices is typically modeled by noise sources at the gate and drain. While consensus exists regarding the origin of the gate noise, that of drain noise is a topic of debate. Here, we report a theory of drain noise as a type of partition noise arising from real-space transfer of hot electrons from the channel to the barrier. The theory accounts for the magnitude and dependencies of the drain temperature and suggests strategies to realize devices with lower noise figure.

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Pt Gate Sink-In Process Details Impact on InP HEMT DC and RF Performance

Cited by 15 publications

References 14 publications

Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs*

Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs*

InAs Channel Inset Effects on the DC, RF, and Noise Properties of InP pHEMTs

Theory of drain noise in high electron mobility transistors based on real-space transfer

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