Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

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“…Recently, pseudo-NMOS inverter has been accepted as the faster design as compared to the conventional inverter [23].…”

Section: Design and Analysis Of Pseudo-nmos Invertermentioning

confidence: 99%

Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Priya

Srivastava

Mishra

2019

Journal of Nanotechnology

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“…Since the SOI devices have better subthreshold characteristics, their leakage currents are also smaller as compared to bulk. [15,16] Thus the static power consumption of SOI circuit is smaller than bulk counterpart. …”

Section: Low Power In Soi Technologymentioning

confidence: 99%

A Theoretical Study of Low Power Soi Technology

Vandana¹

2013

(IOSR-JVSP

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“…In comparison to existing techniques, the suggested multiplier's synthesis results demonstrate a 35.45 % reduction in power consumption, 40.75 percent reduction in area, and 15.65 percent reduction in delay .In [2] pseudo-NMOS was examined in a new light and discovers that SOI technology enables significant performance (speed and power) and area gains, implying that it will be widely used in the design of SOI custom-integrated circuits. As the pseudo NMOS offers advantage in terms of area [2] in this paper we use pseudo-NMOS to build array multiplier. This paper describes the operation of pseudo -NMOS and comparison in terms of transistor for various primitive gates in section II.…”

Section: Introductionmentioning

confidence: 99%

Area Efficient Modified Array Multiplier

Shetty¹,

Kiran²

2021

JUSST

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Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

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Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design

Cited by 15 publications

References 1 publication

Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

A Theoretical Study of Low Power Soi Technology

Area Efficient Modified Array Multiplier

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