Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Priya, Anjali; Srivastava, Nilesh Anand; Mishra, R. A.

doi:10.1155/2019/4935073

Cited by 5 publications

(2 citation statements)

References 22 publications

(36 reference statements)

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“…Compatible with exact industrystandard data reproduction. Two nanodevices were the subject of comparative analysis by Priya et al [28]. To study SCE, an analytical model for V th variation was created.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

2023

IJATEE

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The conventional silicon channel metal oxide semiconductor field effect transistor (MOSFET) has fundamental limits that are reached due to scalability, resulting in short-channel effects (SCE) and other issues in small-channel devices. To overcome these challenges and design a nanoscale device, an alternate material was needed. Graphene, a novel material with exceptional properties, has been utilized to create a graphene field-effect transistor (GFET) optimized using siliconon-insulator (SOI) technology. The SOI structure uses graphene as a channel, resulting in the development of a new silicon-on-insulator graphene field effect transistor (SIGFET) with an 18 nm channel length. The designed SIGFET exhibits significant improvements compared to traditional GFET and MOSFET. Specifically, the subthreshold slope (SS) of the SIGFET is 60.93 mV/decade, the drain-induced barrier lowering (DIBL) is 42.89 mV/V, and the ION/IOFF ratio is 6.55×108, which surpasses previous GFET-based contributions and SOI-MOSFET. Moreover, the effect of temperature change on SIGFET performance has been investigated, revealing that temperature variation only affects the drain current and has no impact on short channel characteristics. Therefore, the SIGFET can be an ideal substitute for traditional silicon channel devices.

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Section: Literature Reviewmentioning

confidence: 99%

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

2023

IJATEE

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“…Amplifiers are used to circumvent the noise of subsequent stage or to provide logic levels to digital circuits. The implementation of novel structures shows great improvement in the CMOS circuit [20][21][22][23]. This section proposes a unique attempt to investigate the drain current, output voltage and voltage gain of common source amplifier.…”

Section: Common Source Amplifiermentioning

confidence: 99%

Thermal Stability Analysis of Graded-Channel Dual-Material Double-Gate (GCDMDG) MOSFET for Analog Application

Priya

Gupta²,

Agrawal

et al. 2021

Lecture Notes in Electrical Engineering

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The advancement of semiconductor industries is a driving force for MOSFET scaling. But as the dimensions of the device are reduced, short channel effects degrade the performance of the device [1]. The scaling of channel length reduces the controllability of gate over the channel region by increasing the charge sharing from source/drain. Due to this, the threshold voltage of MOS device becomes smaller. According to international technology roadmap for semiconductor (ITRS) [2], inclusion of new technologies is turning out to be a critical issue for sub-nanometer MOS devices. Researchers are still working with many device structures to find out a device that can be used in high-frequency application with low power consumption.Since past few decades, the double-gate (DG) MOSFET has shown potential in sub-nanometer regime due to its superb resistance to short channel effects (SCEs) [3]. Researchers have been working with various double-gate structures [4][5][6][7][8][9]. Many theoretical-, simulation-and experimental-based studies have been reported in the literature on DMDG MOSFET. Reddy et al. [10] have reported that the DMDG MOSFET can offer a noteworthy reduction in the hot carrier effects (HCEs). Increased drain breakdown voltage, reduced drain conductance, improved transconductance and desired threshold voltage roll off can be achieved with a DMDG MOSFET below 100 nm channel length. Other than above structures, there are more devices such as quadruple gate [11] MOSFET and Triple Metal Gate Recessed

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Performance Analysis of Gate-Stack Nanoscaled Recessed-S/D SOI-MOSFET for Analog Applications

Srivastava

Priya

Mishra

2021

Lecture Notes in Electrical Engineering

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Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Cited by 5 publications

References 22 publications

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

Thermal Stability Analysis of Graded-Channel Dual-Material Double-Gate (GCDMDG) MOSFET for Analog Application

Performance Analysis of Gate-Stack Nanoscaled Recessed-S/D SOI-MOSFET for Analog Applications

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