The paper explores the analog analysis and higher order derivatives of drain current (I D ) at gate source voltage (V GS ), by introducing channel engineering technique of 3D conventional and Wavy Junctionless FinFETs (JLT) as silicon germanium (Si 1-0.25 Ge 0.25 ) device layer. In view of this, the performances are carried out for different gate length (L G ) values (15-30 nm) and current characteristics determined by maintaining constant ON current (I ON 10 -5 ) (A/μm) for both devices. With respect to this, a comparison has been made between these MOS structures at molefraction x = 0.25 and it was found that the electric field is perpendicular to the current flow which induces volume inversion approach. Accordingly, for the simulation study better channel controllability over the gate is observed for Wavy structures and high I D induces as the L G scales down. With respect to this the constant I ON determine I D , transconductance (g m ), transconductance generation factor (TGF) and its higher order terms (g \ m , and g \\ m ) of the devices are studied with relaxed SiGe approximation. The extensive simulation study on short channel (SC) parameters are also performed and it is observed that the Wavy JL FinFET shows less sensitivity towards short channel effects (SCEs) over conventional one, therefore the dependency of N-type doping concentration (N D = 1.7x10 19 cm -3 ) and metal workfunction (ϕ M = 4.6 eV) are responsible to achieving reduced SCEs.
The work explores the performance estimation of Inverted 'T' (IT) architecture with JL topology i.e (ITJL-FinFET, the device utilizes unwanted area among multi-fins with bulk conduction mechanism) on SOI platform. For the first time, the crucial performance metrics of ITJL FinFET are debated extensively by varying the geometry dimensions at 22-nm node. The gate length (L G ), virtual underlap source (L US ) and drain (L UD ), and workfunction (φ M ) are optimized at 20-nm, 4-nm, 4.6 eV respectively. The SS, DIBL and switching current ratio (I ON /I OFF ) are achieved 69 mV/decade, 27 mV/V and 10 5 . The decrement in transconductance (g m ) with increasing in length of L G , L US , L UD and simultaniously, transconductance generation factor (TGF) tends to improve. Moreover, we have been examine the grid sensitivity of the device and considered the grid points where the independency of I-V characteristics achieved during simulation. The result ensures a systematic prefabrication analysis of ITJL FinFET found to be appropriate, which will overcome the challenges at the nanoscale regime.
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