Inverted ‘T’ Junctionless FinFET (ITJL FinFET): Performance Estimation through Device Geometry Variation

Abstract

The work explores the performance estimation of Inverted 'T' (IT) architecture with JL topology i.e (ITJL-FinFET, the device utilizes unwanted area among multi-fins with bulk conduction mechanism) on SOI platform. For the first time, the crucial performance metrics of ITJL FinFET are debated extensively by varying the geometry dimensions at 22-nm node. The gate length (L G ), virtual underlap source (L US ) and drain (L UD ), and workfunction (φ M ) are optimized at 20-nm, 4-nm, 4.6 eV respectively. The SS, DIBL and switching current ratio (I ON /I OFF ) are achieved 69 mV/decade, 27 mV/V and 10 5 . The decrement in transconductance (g m ) with increasing in length of L G , L US , L UD and simultaniously, transconductance generation factor (TGF) tends to improve. Moreover, we have been examine the grid sensitivity of the device and considered the grid points where the independency of I-V characteristics achieved during simulation. The result ensures a systematic prefabrication analysis of ITJL FinFET found to be appropriate, which will overcome the challenges at the nanoscale regime.

Design and Simulation of Dielectrically Modulated Dual Material Gate-Stack Double-Gate FinFET Biosensor

“…This work raised the use of the high-K spacer material to improve upon the drawback in the conventional DG-GS-FinFET. 13,26,27 The integration of the spacer has been a long-time challenge. However, the spacer material may help increase the convergence of the fringing field in the underlap region, improving the analog and RF performances, by overcoming problems, such as V TH pinning, mobility degradation, poor reliability, thermal budget, etc.…”