PRR-PRR Dynamic Relocation

Sudarsanam, Arvind; Kallam, Ramachandra; Dasu, Aravind

doi:10.1109/l-ca.2009.49

Cited by 16 publications

(7 citation statements)

References 8 publications

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“…This filter realizes the necessary manipulation to modify the position of the configured functionality when the bitstream is being downloaded from off-chip memory. The authors in [6] proposed an algorithm named PRR-PRR to obtain the relocation of a bitstream. The basic idea behind this algorithm is to change the bitstream frame by frame.…”

Section: A Related Workmentioning

confidence: 99%

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Hannachi¹,

Rabah²,

Jovanovic³

et al. 2014

2014 26th International Conference on Microelectronics (ICM)

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Adaptive systems based on FPGA architectures can benefit greatly from the high degree of flexibility offered by Dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. The limitations in the existing tools provided by major FPGA manufacturers do not allow an efficient placement and relocation of variable-sized hardware tasks. This paper presents a design method for relocation of variable-sized hardware task on SRAM-based FPGAs for adaptive systems using dynamic partial reconfiguration (DPR). The proposed relocation procedure takes into account the communication between different reconfigurable regions and static region. This work gives a detailed description of the proposed partial bitsream relocation of variable-sized hardware tasks targeting the Virtex-5 FPGAs.

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Section: A Related Workmentioning

confidence: 99%

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Hannachi¹,

Rabah²,

Jovanovic³

et al. 2014

2014 26th International Conference on Microelectronics (ICM)

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“…This software component contains the read/modify/write operation for configuration data, which enables fine-grain hardware modification, like changing LUT equations, as well as copying a rectangular region of configuration memory and pasting it in another position. This can be very useful to some applications, avoiding the access to the external memories The PRR-PRR reconfiguration approach introduced in [19], provides frame relocating from a partial reconfigurable region (PRR) in the device, into another region. This is done in a frame by frame basis, in order to accelerate the relocation process and to reduce the bitstream storing requirements.…”

Section: Reconfiguration Engine Requirementsmentioning

confidence: 99%

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Otero

Llinás

Lombardo

et al. 2011

VLSI Circuits and Systems V

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Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families.

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“…The PRR-PRR reconfiguration approach introduced in [21], provides frame relocating from a partial reconfigurable region (PRR) in the device, into another region. This is done in a frame by frame basis, in order to accelerate the relocation process and to reduce the bitstream storing requirements.…”

Section: State Of the Artmentioning

confidence: 99%

A Modular Peripheral to Support Self-Reconfiguration in SoCs

Otero¹,

Morales-Cas²,

Portilla³

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Abstract-In this paper, a solution to support the run-time readback, relocation and replication of cores in embedded systems with dynamic and partial reconfiguration capabilities is presented. The proposal shows a peripheral structure that allows an easy integration and communication with the rest of the system, including an API to make the reconfiguration details to be more transparent to software applications. Differently to other proposals, all functionality is implemented in hardware, achieving a higher reconfiguration speed. In addition, different design decisions have been taken in order to increase the portability of the solution to existing and, possibly, future FPGAs. Finally, a use case is provided, which shows the features of this module applied to the run-time scaling of a hardware coprocessor.

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PRR-PRR Dynamic Relocation

Cited by 16 publications

References 8 publications

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

A Modular Peripheral to Support Self-Reconfiguration in SoCs

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