A Modular Peripheral to Support Self-Reconfiguration in SoCs

Abstract

Abstract-In this paper, a solution to support the run-time readback, relocation and replication of cores in embedded systems with dynamic and partial reconfiguration capabilities is presented. The proposal shows a peripheral structure that allows an easy integration and communication with the rest of the system, including an API to make the reconfiguration details to be more transparent to software applications. Differently to other proposals, all functionality is implemented in hardware, achieving a higher reconfiguration speed. In addition, different design decisions have been taken in order to increase the portability of the solution to existing and, possibly, future FPGAs. Finally, a use case is provided, which shows the features of this module applied to the run-time scaling of a hardware coprocessor.

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

“…The solution for bitstream relocation proposed in this paper is a version of a former one proposed in [4], ported to Spartan-6 devices. It can be considered like a hardware-based one, with enhanced functionality.…”

“…The first option is a low area-consumption and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic that achieves a much faster reconfiguration speed. This reconfiguration hardware block was originally designed to the Virtex-5 family [4], and its porting process will also be described in this work, facing the interoperability problem among different families. In addition, the performance of the reconfigurable platform has been evaluated, considering both the reconfiguration time and its implication in the power consumption.…”

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

“…Consequently, final PE position in the device is not predefined. Differently, as shown in [11], header and tail info, as well as frame addresses, are added at run time. This strategy provides two advantages: i) A reduction of the bitstream size that allows reducing the whole data transference time from the external memory, and ii) faster relocation possibilities.…”

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

“…Details about the reconfiguration process are outside the scope of this work. It is carried out by means of an Internal Configuration Access Port (ICAP) controller described in [25], which includes specific features to allow module relocation, specifically addressing these kinds of scalable application. Through the regularity of the architecture, and making use of the DPR, only 8 different bitstream files are enough for configuring any m×n size.…”