Prototype implementation and evaluation of a multibank embedded memory architecture in programmable logic

Huang, Jin; Manjikian, Naraig

doi:10.1109/pacrim.2003.1235707

2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) (Cat. No.03CH37490)

DOI: 10.1109/pacrim.2003.1235707

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Prototype implementation and evaluation of a multibank embedded memory architecture in programmable logic

Jin Huang

Naraig Manjikian

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A dual round-robin arbiter for split-transaction buses in system-on-chip implementations

Reed

Manjikian

Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513)

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Prototype implementation and evaluation of a multibank embedded memory architecture in programmable logic

Cited by 3 publications

References 3 publications

A dual round-robin arbiter for split-transaction buses in system-on-chip implementations

A dual round-robin arbiter for split-transaction buses in system-on-chip implementations

Cache coherence support in a split-transaction bus for prototyping of system-on-chip multiprocessors

A user-configurable framework for testing prototype system-on-chip implementations

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