A dual round-robin arbiter for split-transaction buses in system-on-chip implementations

Reed, J.; Manjikian, Naraig

doi:10.1109/ccece.2004.1345244

Cited by 8 publications

(3 citation statements)

References 3 publications

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“…Previously, a Dual Round Robin Arbiter (DRRA) is designed to split the transaction bus in SoC implementation [14]. The data bus arbiter and address bus arbiter are used to construct a non-multiplexed transaction bus.…”

Section: Related Workmentioning

confidence: 99%

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Singh

Ravindra²,

Naik

2022

IJIE

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Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic-based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA). The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm technology. The proposed CPLA is suitable for compact and smart applications with glitch free and fair arbitration. The proposed CPLA presents 41.2% reduction in total area consumption. It also provides 47.12% average Area and Power Product (APP) reduction when compared to the existing 4-bit PLA. Similarly, the proposed 8-bit CPLA shows 49.48% average APP product shrinkage when compared to conventional 8-bit PLA. For low power and area constraint applications, the proposed CPLA with EGDI is best in comparison to the static CMOS based ping lock round robin arbiter. Therefore, the results demonstrate that the proposed CPLA achieves low power and consumes less area than the existing ping lock arbiter.

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Section: Related Workmentioning

confidence: 99%

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Singh

Ravindra²,

Naik

2022

IJIE

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“…Crossbar switching bus allows more than one bus operation proceeded simultaneously [2] . A split-transaction bus can decouple requests from responses, so the shorter latency responses is finished [3] .This paper presents a bus architecture named XDPB which achieve a high throughput by adopting crossbar bus topology in data bus and low bus latency by split transaction buses with separate address and data lines. The distributed arbitration strategy is adopted in the architecture.…”

Section: Introductionmentioning

confidence: 98%

A parallel low latency bus on chip for packet processing MPSoC

Liu

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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In this paper an bus architecture combining crossbar switching with split transaction feature is presented for multiprocessor system on chip (MPSoC) in the packet processing application. The high throughput is achieved with crossbar bus topology and low bus latency is finished by split transaction buses which separate address bus from data one. Experimental results show that performance of the proposed architecture is improved up to 2.3 times than the one of the AHB buses and reduce communication latency about 45% than the later. Moreover, the bus arbiter implementation has reasonable area and timing cost which make it suitable for high performance IP-packet or base-band processing.

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“…In system-on-chip (SoC) implementations, the transaction buses are split by designing a dual RRA [3]. A non-multiplexed rip-transaction bus is constructed using an address bus arbiter and data bus arbiter for SoC implementation.…”

Section: Introductionmentioning

confidence: 99%

Design of matrix, distributive round robin, ping pong and enhanced ping lock arbiter for shared resources systems

Lakshminarayanan Venkatara,

Sumithra,

Purushothaman

et al. 2023

IJEECS

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Arbiter is one of the main core elements in the network scheduler. The significant goal of this work is to design a high-speed and low execution-time arbiter with lock free and fair arbitration scheme. In this work, four types of arbiters such as matrix arbiter (MA), ping pong arbiter (PPA), distributive round-robin arbiter (DRRA) and enhanced ping lock arbiter (EPLA) are designed and analyzed area, delay, and speed of arbiters. MA is worked in square matrix format and matrix transition is performed for effective routing. The DRRA is designed by using a multiplexer and counter. Hence an, effective scheduling is carried out in DRRA. Binary tree format is used in PPA. The PPA provides low chip size and high speed than existing MA and DRRA. The PPA limits fair arbitration during uniformly distributed active request patterns. To overcome this problem, PPA is improved with some lock systems to create an EPLA. A new ping lock arbiter (PLA) leaf and PLA inter structure is proposed at the gate level to reduce the execution delay, improve the speed and achieve fair arbitration over all other existing arbiters. Resource allocation, execution delay, and speed are analyzed using the Xilinx Integrated Software Environment (ISE) tool.

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A dual round-robin arbiter for split-transaction buses in system-on-chip implementations

Cited by 8 publications

References 3 publications

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

A parallel low latency bus on chip for packet processing MPSoC

Design of matrix, distributive round robin, ping pong and enhanced ping lock arbiter for shared resources systems

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