Prototype hardware implementation of a single-chip multiprocessor with a split-transaction bus

Manjikian, Naraig; Reed, J.

doi:10.1109/pacrim.2005.1517311

Cited by 4 publications

(2 citation statements)

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“…In future work, each node element will be based on a previously-developed custom cache-coherent multiprocessor with a split-transaction bus [10], rather than on single noncache-coherent Altera processors. QUI 2 VER has also been used to create the aforementioned custom multiprocessor [9], hence it would be easily integrated into the tool chain.…”

Section: Discussionmentioning

confidence: 99%

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High-level specification and logic implementation of single-chip multiprocessor systems based on a configurable router

Pau

Manjikian

2008

2008 Canadian Conference on Electrical and Computer Engineering

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This paper describes prototype implementations of single-chip multiprocessor systems with a configurable router intended for dedicated, embedded network-on-chip support within fieldprogrammable gate arrays in order to provide performance and flexibility for system-on-chip applications. The router supports ring, octagon, and mesh network topologies. Implementation in an Altera Stratix EP1S80 chip is supported with a tool chain that combines custom high-level system specification software with commercial Altera software to generate single-chip multiprocessors using multiple instances of the configurable router and the Altera Nios II soft processor. A 16-node multiprocessor using a mesh topology occupies up to two-thirds of an Altera Stratix EP1S80 chip, and the aggregate communication bandwidth for a mesh is experimentally shown to be at least 11.5 Gbytes/sec with an 80-MHz system clock and 64-bit-wide connections.

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Section: Discussionmentioning

confidence: 99%

“…The node element will ultimately consist of a custom cache-coherent multiprocessor subsystem with a true split-transaction bus, as developed in earlier work [10].…”

Section: Sopc Builder For Node Generationmentioning

confidence: 99%