Protocol selection and interface generation for HW-SW codesign

Abstract

The aim of this paper is to present a communication synthesis approach stated as an allocation problem. In the proposed approach, communication synthesis allows to transform a system composed of processes that communicate via high-level primitives through abstract channels into a set of processes executed by interconnected processors that communicate via signals and share communication control. The proposed communication synthesis approach deals with both protocol selection and interface generation and is based on binding/allocation of communication units. This approach allows a wide design space exploration through automatic selection of communication protocols. We present a new algorithm that performs binding/allocation of communication units. This algorithm makes use of a cost function to evaluate different allocation alternatives. We illustrate through an example the usefulness of the algorithm for allocating automatically different protocols within the same application system

Interface synthesis: issues and approaches

“…Implementation selection gives a cost effective solution to implement the selected protocol. Daveau et al [3] and Knudsen et al [9] follow this approach.…”

“…Approach in [11] is applicable for m to n, continuous/discontinuous, buffered, shared channel. In [3] and [9] features depend on the library support available.…”

“…• simulation is modular, and easier • large design space exploration possible While [16], [13], and [11] work at word transfer level, [3] and [9] start at message passing level and refine it subsequently.…”

“…In this approach by Daveau et al [3] at TIMA/INPG Laboratory, Institut Polytechnique de Grenoble, France, design space exploration is carried out to optimize the use of resources and to minimize the cost by solving communication synthesis problem as an equivalent allocation problem. Algorithm described in the paper makes use of a cost function to evaluate different allocation alternatives.…”

Interface synthesis using memory mapping for an FPGA platform

“…However, the use of memory mapping for interface synthesis has not been considered. Furthermore, hardware-software co-design methodologies that synthesize the hardware component as an ASIC, pay little attention towards optimizing the memory mapping since the amount of logic that can be mapped to an ASIC is less severely constrained than that for FPGAs [2,7,8].…”