Interface synthesis using memory mapping for an FPGA platform

Luthra, Manev; Gupta, Sumit Kumar; Dutt, Nikil; Gupta, Rajesh K.; Nicolau, Alexandru

doi:10.1109/iccd.2003.1240886

Cited by 14 publications

(10 citation statements)

References 20 publications

(14 reference statements)

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“…Although some tools support memory accesses whose ordering dependences are statically determinable [3], [13], [19], [28]- [31], the memory-interface design is quite different from our solution. Since all memory accesses are always statically scheduled in these approaches, contention between memory accesses is statically reduced or eliminated.…”

Section: B Architecture Supportmentioning

confidence: 89%

“…In [19] and [30], memory accesses are bus based; in [30], memory operations are statically scheduled and will never contend for the bus, while in [19], a global controller selects memory accesses from several FIFOs in a roundrobin fashion. Luthra et al [13] allow concurrent accesses to multiple memory banks, but they place important restrictions on the input language to be able to partition the memory into separate banks. Huang et al [29] rely on a platform-based architecture that obviates the need for elaborate memory-access interfaces that must support concurrence.…”

Section: B Architecture Supportmentioning

confidence: 99%

“…1) Memory-size estimation and mapping: A vast body of work examines the ideal sizing of memory modules in order to customize them to the particular application's needs [9]- [13]. Séméria et al [14] described how data structures in ANSI-C can be allocated into separate memories.…”

Section: A Specification Supportmentioning

confidence: 99%

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Hardware compilation of application-specific memory-access interconnect

Venkataramani

Bjerregaard

Chelcea

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA's application-specific MAN construction significantly improves power and performance for a range of benchmarks.Index Terms-Communication synthesis, dataflow synthesis, high-level synthesis (HLS), interface design.

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Section: B Architecture Supportmentioning

confidence: 89%

Section: B Architecture Supportmentioning

confidence: 99%

See 1 more Smart Citation

Hardware compilation of application-specific memory-access interconnect

Venkataramani

Bjerregaard

Chelcea

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…There has been research that focuses on the synthesis for minimizing register file (or memory module) numbers or port numbers, so that the interconnects can be optimized indirectly. In [Luthra et al 2003] the authors proposed a hardware/software co-synthesis approach to allocate data to shared memories on FPGAs. Their algorithm uses lifetime information produced by a scheduling algorithm and minimizes the number of memory instances in order to simplify multiplexors indirectly.…”

Section: Related Work and Our Contributionmentioning

confidence: 99%

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

Cong

Fan²,

2009

ACM Trans. Des. Autom. Electron. Syst.

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Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource binding approach based on a distributed register-file microarchitecture (DRFM), which makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared to the traditional discrete-register counterpart, a DRFM allows use of the platformfeatured on-chip memory or register-file IP blocks to implement its local register files, and this results in a substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Given the scheduling solution and resource (functional units) constraints, two novel algorithms in the resource binding stage are developed based on DRFM: (i) A simultaneous DRFM clustering and binding algorithm, which decides the configuration of DRFM and the assignment of operations into islands with the focus on optimizing global connections; (ii) A data-forwarding scheduling algorithm, which takes advantage of the operation slacks to handle the read-port restriction of register files. On the Xilinx Virtex4 FPGA platform, experimental results with a set of real-life test cases show a 50% logic area reduction achieved by applying our approach, with a 14.6% performance improvement, compared to the traditional discrete-register-based approach. Also, experiments on small-size designs show that our algorithm produces the same number of total connections and at most one more maximum feeding-in connection compared to optimal solutions generated by ILP.

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“…Network-based communications To model the communications cost, a communication class must be selected according to the target architecture. In general, the model should include one or more of the following cost terms [Luthra et al 2003]: 1. Hardware cost: The area needed to implement the HW/SW interface and associated data transfer delay on the hardware side.…”

Section: Communications Cost Modelingmentioning

confidence: 99%