Protecting SRAM-based FPGAs against multiple bit upsets using erasure codes

Rao, Parthasarathy M. B.; Ebrahimi, Mojtaba; Seyyedi, Razi; Tahoori, Mehdi B.

doi:10.1109/dac.2014.6881539

Cited by 11 publications

(7 citation statements)

References 19 publications

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“…Other soft error studies related to multiple upsets include MBU effects on SRAM-based field-programmable gate arrays (FPGAs) [30], [31] and temporary multi-node upsets in combinational logic cells [32].…”

Section: Related Workmentioning

confidence: 99%

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

Cho

Kwon

2019

IEEE Access

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Transient errors induced by radiations cause bit-flips in flip-flops (flip-flop soft errors).Modeling the error resilience level of a target system for flip-flop soft errors is a crucial step to achieve a costeffective error resilience solution. This step often requires a significant amount of time and effort for a large number of fault injection simulations. As technology scales, the required effort grows in a new dimension with the increased probability of multi-bit upsets (MBUs). In this work, we present a new estimation model that predicts the resulting error resilience levels for the flip-flop MBU cases. This estimation model only requires the measured soft error effects of the single-bit upset (SBU) cases. This model uses two strategies to address how multiple bit-flips that happen simultaneously in a system affects the outcome of application execution. We evaluate the accuracy level of the MBU estimation model using actual fault injection results on two different processor cores. The two main strategies in our estimation model improve the accuracy levels by more than 7×.

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Section: Related Workmentioning

confidence: 99%

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

Cho

Kwon

2019

IEEE Access

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“…Authors in [6] proposed a Duplication With Recovery (DWR) technique to correct soft error in an FPGA configuration memory for bits meant for routing resources, which contribute to the majority of soft errors in FPGAs and are most vulnerable to single event upset because they consume most area and seventy to ninety percent of the configuration bits are attributed to the routing resources. In [8] the authors proposed a scrubbing scheme which reconstructs erroneous configuration memory frame based on the concept of erasure codes. The erasure codes recovers the original frame when some of the bits are flipped.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Thus, when a fault changes the state of an SRAM cell, this event is referred as SEU [7]. In other words, SRAM-based FPGAs are more prone to soft errors since a radiation strike in a configuration memory has a permanent effect on the functionality of the mapped design [8]. The SRAM-based FPGAs are especially sensitive to SEUs within the configuration memory of the device.…”

Section: Introductionmentioning

confidence: 99%

An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA

Haruna¹,

Abubilal²,

Salawudeen³

2017

IJCA

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The use of Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance. However, SRAM-based FPGAs are susceptible to radiation induced Single Event Upset (SEU) that affects the functionality of the implemented design. Therefore, an improved Frame Level Redundancy (FLR) algorithm that uses Cyclic Redundancy Check (CRC) as an error detection technique for configuration memory scrubbing, is developed as a solution to mitigate SEU through upset detection and correction. Fault injection was performed on FPGA configuration memory frames on different number of modules to emulate SEU. The improved FLR algorithm was implemented and system level simulation was carried out using MATLAB. The performance of the improved FLR algorithm was compared with that of the existing FLR algorithm using error correction time and energy consumption as metrics. The results of this work showed that the improved FLR algorithm produced 31.6% improvement in error correction time and 61.1% improvement in energy consumption over the existing FLR algorithm.

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“…Now a days different parity check codes are used intelligently in MBU correction. Parthasarathy et.al use interleaved parity check code along with scrubbing against MBU in SRAM based FPGA in [18].…”

Section: Background and Related Workmentioning

confidence: 99%

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Mandal

Paul

et al. 2016

IEEE Embedded Syst. Lett.

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Field Programmable Gate Arrays (FPGAs) are more prone to be affected by transient faults in presence of radiation and other environmental hazards compared to Application Specific Integrated Circuits (ASICs). Hence, error mitigation and recovery techniques are absolutely necessary to protect the FPGA hardware from soft errors arising due to such transient faults. In this paper, a new efficient multi-bit error correcting method for FPGAs is proposed using adaptive cross parity check (ACPC) code. ACPC is easy to implement and the needed decoding circuit is also simple. In the proposed scheme total configuration memory is partitioned into two parts. One part will contain ACPC hardware, which is static and assumed to be unaffected by any kind of errors. Other portion will store the binary file for logic, which is to be protected from transient error and is assumed to be dynamically reconfigurable (Partial reconfigurable area). Binary file from the secondary memory passes through ACPC hardware and the bits for forward error correction (FEC) field are calculated before entering into the reconfigurable portion. In the runtime scenario, the data from the dynamically reconfigurable portion of the configuration memory will be read back and passed through the ACPC hardware. The ACPC hardware will correct the errors before the data enters into the dynamic configuration memory. We propose a first of its kind methodology for novel transient fault correction using ACPC code for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like critical path, power consumption, overhead resource and error correction efficiency to estimate the performance of our proposed method.

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Protecting SRAM-based FPGAs against multiple bit upsets using erasure codes

Cited by 11 publications

References 19 publications

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

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