A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Abstract

Field Programmable Gate Arrays (FPGAs) are more prone to be affected by transient faults in presence of radiation and other environmental hazards compared to Application Specific Integrated Circuits (ASICs). Hence, error mitigation and recovery techniques are absolutely necessary to protect the FPGA hardware from soft errors arising due to such transient faults. In this paper, a new efficient multi-bit error correcting method for FPGAs is proposed using adaptive cross parity check (ACPC) code. ACPC is easy to implement and the needed decoding circuit is also simple. In the proposed scheme total configuration memory is partitioned into two parts. One part will contain ACPC hardware, which is static and assumed to be unaffected by any kind of errors. Other portion will store the binary file for logic, which is to be protected from transient error and is assumed to be dynamically reconfigurable (Partial reconfigurable area). Binary file from the secondary memory passes through ACPC hardware and the bits for forward error correction (FEC) field are calculated before entering into the reconfigurable portion. In the runtime scenario, the data from the dynamically reconfigurable portion of the configuration memory will be read back and passed through the ACPC hardware. The ACPC hardware will correct the errors before the data enters into the dynamic configuration memory. We propose a first of its kind methodology for novel transient fault correction using ACPC code for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like critical path, power consumption, overhead resource and error correction efficiency to estimate the performance of our proposed method.

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

“…Many researchers have proposed different techniques to manage soft errors in FPGAs. [10][11][12][13][14][15] Adewale Adetomi et al [10], designed ICAP Controller with a selective-area soft error Mitigation Engine. They tried to scan selective-area of the FPGA instead of entire device which saved them the time available for reconfiguration.…”

“…This was the limitation. Swagata Mandal [11] have proposed a new error correcting code to protect configuration memory of FPGAs from soft error, which gives better performance compared to the other commonly used error correcting codes. They also proposed hardware architecture with partial reconfiguration for the designed code.…”

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

“…These ad-hoc techniques can be divided into Algorithmic-Based Fault-Tolerance Techniques (ABFT), in which the error detection is achieved by exploiting arithmetic properties of the algorithm [19], [20], and techniques based on exploiting structural properties of the design to create a protection scheme [16]. Other approaches, which are out of the scope of this paper, are based on analog circuits that give support to digital designs to detect faulty behaviors [21] and powerful error correction codes to protect the FPGA hardware from soft errors, which involve iterative processes at a larger timing cost [22], [23].…”