Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes

Rao, Parthasarathy M. B.; Ebrahimi, Mojtaba; Seyyedi, Razi; Tahoori, Mehdi B.

doi:10.1145/2593069.2593191

Cited by 18 publications

(11 citation statements)

References 21 publications

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“…Several works [37]- [39] show that the incidence of errors due to radiation or heat occurs within a neighborhood. For example, in the region of a radiation event, more than one neighboring cell may have its content changed.…”

Section: Ecc Mappingmentioning

confidence: 99%

“…Figure 15 illustrates that the error pattern is inserted in a region consisting in a reference cell (in red), which is virtually surrounded by an inner rectangle of cells (in green) that is wrapped by an outer rectangle of cells (in blue); thus, an error pattern can comprise from one to 25 error cells. This work follows the assumptions for the error pattern generation based on the neighborhood models [37]- [39]:…”

Section: Ecc Mappingmentioning

confidence: 99%

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LPC: An Error Correction Code for Mitigating Faults in 3D Memories

Freitas

Mota

Marcon

et al. 2021

IEEE Trans. Comput.

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The radiation sensitivity of memory cells increases dramatically as CMOS manufacture technology scales down; therefore, the reliability of memories has become a challenge. 3D technology has gained attention for having several advantages compared to the 2D counterpart, such as high integration density, high performance, low power, and high communication speed. Although several studies are targeting 3D memories, the effects on reliability using this technology have received little attention. This work introduces Line Product Code (LPC), a modified product code-based Error Correction Code (ECC) that uses both Hamming and parity in both rows and columns to implement reliable 3D memories. We implemented two lightweight LPC-based decoding algorithms in interleaved (LPCa-I) and non-interleaved (LPCa) versions, which allowed us to analyze LPC through a set of simulation cases that considers four severity levels of error incidence. The experimental results showed the effectiveness of the LPC-based algorithms, reaching correction rates of up 2.3 times higher compared to other Hamming-based algorithms.

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Section: Ecc Mappingmentioning

confidence: 99%

Section: Ecc Mappingmentioning

confidence: 99%

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

Freitas

Mota

Marcon

et al. 2021

IEEE Trans. Comput.

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“…Now a days different parity check codes are used intelligently in MBU correction. Parthasarathy et.al use interleaved parity check code along with scrubbing against MBU in SRAM based FPGA in [18].…”

Section: Background and Related Workmentioning

confidence: 99%

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Mandal

Paul

et al. 2016

IEEE Embedded Syst. Lett.

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Field Programmable Gate Arrays (FPGAs) are more prone to be affected by transient faults in presence of radiation and other environmental hazards compared to Application Specific Integrated Circuits (ASICs). Hence, error mitigation and recovery techniques are absolutely necessary to protect the FPGA hardware from soft errors arising due to such transient faults. In this paper, a new efficient multi-bit error correcting method for FPGAs is proposed using adaptive cross parity check (ACPC) code. ACPC is easy to implement and the needed decoding circuit is also simple. In the proposed scheme total configuration memory is partitioned into two parts. One part will contain ACPC hardware, which is static and assumed to be unaffected by any kind of errors. Other portion will store the binary file for logic, which is to be protected from transient error and is assumed to be dynamically reconfigurable (Partial reconfigurable area). Binary file from the secondary memory passes through ACPC hardware and the bits for forward error correction (FEC) field are calculated before entering into the reconfigurable portion. In the runtime scenario, the data from the dynamically reconfigurable portion of the configuration memory will be read back and passed through the ACPC hardware. The ACPC hardware will correct the errors before the data enters into the dynamic configuration memory. We propose a first of its kind methodology for novel transient fault correction using ACPC code for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like critical path, power consumption, overhead resource and error correction efficiency to estimate the performance of our proposed method.

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“…Since adjacent memory cells are distributed over several data segments, multiple bit upsets can be detected and corrected. A recent work that advances this concept is proposed in [Rao et al 2014]. Here, the process of detecting multiple bit upsets and correcting them is separated.…”

Section: Configuration Memorymentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes

Cited by 18 publications

References 21 publications

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

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