Protecting Private Keys against Memory Disclosure Attacks Using Hardware Transactional Memory

Abstract

Cryptography plays an important role in computer and communication security. In practical implementations of cryptosystems, the cryptographic keys are usually loaded into the memory as plaintext, and then used in the cryptographic algorithms. Therefore, the private keys are subject to memory disclosure attacks that read unauthorized data from RAM. Such attacks could be performed through software methods (e.g., OpenSSL Heartbleed) even when the integrity of the victim system's executable binaries is maintained. They could also be performed through physical methods (e.g., cold-boot attacks on RAM chips) even when the system is free of software vulnerabilities. In this paper, we propose Mimosa that protects RSA private keys against the above software-based and physical memory attacks. When the Mimosa service is in idle, private keys are encrypted and reside in memory as ciphertext. During the cryptographic computing, Mimosa uses hardware transactional memory (HTM) to ensure that (a) whenever a malicious process other than Mimosa attempts to read the plaintext private key, the transaction aborts and all sensitive data are automatically cleared with hardware mechanisms, due to the strong atomicity guarantee of HTM; and (b) all sensitive data, including private keys and intermediate states, appear as plaintext only within CPU-bound caches, and are never loaded to RAM chips.To the best of our knowledge, Mimosa is the first solution to use transactional memory to protect sensitive data against memory disclosure attacks. We have implemented Mimosa on a commodity machine with Intel Core i7 Haswell CPUs. Through extensive experiments, we show that Mimosa effectively protects cryptographic keys against various attacks that attempt to read sensitive data from memory, and it only introduces a small performance overhead.

CaSE: Cache-Assisted Secure Execution on ARM Processors

“…Register based [24], [22] Cache-based [26], [55], [18] On-Chip Memory Based [18] CaSE 3) Secure Information Flow: It is critical to secure the information flow between the external DRAM and the onchip memory when adopting CaSE on other platforms. Our implementation on the i.MX53 relies on the isolation provided by TrustZone and the ability to lock memory contents in cache to prevent malicious attacks.…”

“…Several research works [24], [22], [23], [77] use register to store cryptographic sensitive materials. In [25], [26], [18], [55], the sensitive cryptographic materials are stored in the processor cache. Alternatively, OCRAM is used in [18].…”

Protecting Suspended Devices from Memory Attacks

“…Some approaches focus exclusively on the protection of a specific encryption key stored in RAM, e.g., the FDE key, but leave all other data in main memory unprotected from memory attacks. Approaches for x86 [25,12,13,23], as well as for ARM [11] and hypervisors exist [26]. Their common idea is to store a key in the CPU/GPU registers or in the CPU cache and to implement the cipher associated with the key on-chip at the cost of system performance.…”

Protecting Sensitive Information in the Volatile Memory from Disclosure Attacks

“…The second category of the proposed solutions for memory encryption is based on hardware modifications. In particular, several publications [18][19][20][21][22][23] [40] for single processor systems propose the addition of an encryption unit to cipher and decipher data from and to the volatile memory. Moreover, for multiprocessor systems, [24] proposes a shared bus, containing a crypto engine, to coordinate and secure traffic between processors, while [25] [26] proposed the use of sequence numbers for the coordination between different processors.…”