Properties of Quantum Templates

Rahman, Md. Mazder; Dueck, Gerhard W.

doi:10.1007/978-3-642-36315-3_10

Cited by 12 publications

(8 citation statements)

References 12 publications

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“…Abdessaied et al [29] used Boolean satisfiability for template matching. In the work performed in [30], a systematic method of generating all templates with a given number of lines was presented.…”

Section: Templates For Logic Synthesismentioning

confidence: 99%

Physical synthesis of quantum circuits using templates

Mirkhani

Mohammadzadeh

2016

Quantum Inf Process

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Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of "physical synthesis" was introduced for quantum circuit flow, and a few techniques were proposed for it. Following that concept, in this paper a new approach for physical synthesis inspired by template matching idea in quantum logic synthesis is proposed to improve the latency of quantum circuits. Experiments show that by using template matching as a physical synthesis approach, the latency of quantum circuits can be improved by more than 23.55 % on average.

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Section: Templates For Logic Synthesismentioning

confidence: 99%

Physical synthesis of quantum circuits using templates

Mirkhani

Mohammadzadeh

2016

Quantum Inf Process

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“…Abdessaied et al [27] used Boolean satisfiability for template matching. In the work performed in [28], a systematic method of generating all templates with a given number of lines was presented. Bandyopadhyay et al [29] proposed a post-synthesis optimization technique for reversible circuits based on newly defined templates.…”

Section: Related Workmentioning

confidence: 99%

A Transformation-Based Quantum Physical Synthesis Approach for Nearest-Neighbor Architectures

Hoseinimanesh

Mohammadzadeh

2021

Quantum Reports

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The physical synthesis concept for quantum circuits, the interaction between synthesis and physical design processes, was first introduced in our previous work. This concept inspires us to propose some techniques that can minimize the number of extra inserted SWAP operations required to run a circuit on a nearest-neighbor architecture. Minimizing the number of SWAP operations potentially decreases the latency and error probability of a quantum circuit. Focusing on this concept, we present a physical synthesis technique based on transformation rules to decrease the number of SWAP operations in nearest-neighbor architectures. After the qubits of a circuit are mapped onto the physical qubits provided by the target architecture, our procedure is fed by this mapping information. Our method uses the obtained placement and scheduling information to apply some transformation rules to the original netlist to decrease the number of extra SWAP gates required for running the circuit on the architecture. We follow two policies in applying a transformation rule, greedy and simulated-annealing-based policies. Simulation results show that the proposed technique decreases the average number of extra SWAP operations by about 20.6% and 24.1% based on greedy and simulated-annealing-based policies, respectively, compared with the best in the literature.

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“…Currently, all templates with three lines and up to 12 gates have been generated. It has been proven that templates with three lines cannot have more than 17 gates [44]. The Hasse diagram enables the search to be guided, avoiding the checking of gates that cannot be moved together according to the moving rule.…”

Section: Template Matchingmentioning

confidence: 99%

“…Recently, a detailed study of the properties of templates has been published [44]. These properties lead to a method to construct all the templates with a certain number of lines.…”

Section: Template Matchingmentioning

confidence: 99%

“…These properties lead to a method to construct all the templates with a certain number of lines. Thus far, the efforts have been focused on quantum templates [44], but it is clear that a similar method can be developed for the MCT templates. Two facts are noteworthy: A complete set of templates can be generated from optimal circuits. If all the templates of a certain size are known, then the optimal circuit (with the same number of lines) can be found by template matching. The first fact is a double edged sword: optimal circuits are required to find optimal circuits.…”

Section: Template Matchingmentioning

confidence: 99%

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Challenges and advances in Toffoli network optimisation

Dueck

2014

IET Computers & Digital Techniques

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This study gives a brief overview of the current trends in reversible logic synthesis with emphasis on template matching. The basic building block for reversible circuits considered here is the multiple-control Toffoli gate. Some approaches to synthesis are reviewed and the challenges are explained. Since many practical functions are not reversible, they must be embedded into reversible ones, if they are to be implemented using reversible logic. The complexity of such embeddings is expounded. A two phase synthesis is described where particular attention is devoted to the optimisation phase via template matching. Insights into the properties of the templates, have led to algorithms that aid the generation of templates. Until recently, the application of templates has been guided by different heuristics. A review of an exact template matching algorithm with a discussion of the implications of such an algorithm is given. Exact matching affects both the generation as well as the application of templates. Results from a prototype implementation are encouraging.

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Properties of Quantum Templates

Cited by 12 publications

References 12 publications

Physical synthesis of quantum circuits using templates

Physical synthesis of quantum circuits using templates

A Transformation-Based Quantum Physical Synthesis Approach for Nearest-Neighbor Architectures

Challenges and advances in Toffoli network optimisation

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