Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs

Bidmeshki, Mohammad Mahdi; Antonopoulos, Angelos; Makris, Yiorgos

doi:10.1109/jetcas.2021.3075098

Cited by 8 publications

(7 citation statements)

References 29 publications

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“…Commonly, these models are simulated in conjunction with the corresponding transistor-level circuit to ensure consistency of the models with the actual implementation of the circuit. [46]. The memristor model, a connect module, provides two ports and has a behavioral description stating the transformation process.…”

Section: Simulation Results Of the Two Schemesmentioning

confidence: 99%

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Zhao

Wang

et al. 2021

Electronics

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Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield α ≥ 5%, or the reading noise σ ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.

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Section: Simulation Results Of the Two Schemesmentioning

confidence: 99%

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Zhao

Wang

et al. 2021

Electronics

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“…The proposed HT relies on performing small malicious modifications in the digital section of the RF transceiver, i.e., DSP and IP core from which the information is being leaked. If the attack is staged by an EDA tool provider or if the digital section of the RF transceiver is a 3PIP core, then the owner of the RF transceiver can check for the presence of the HT prior to fabrication using: (a) functional verification of the 3PIP cores [39]; (b) structural analysis of Hardware Description Language (HDL) codes [39]; (c) logic testing tools [35], [40], [41], [42], [43], [44]; (d) specific simulation benches, i.e., performing aging simulations along with overclocking [45] or short-term aging [46] to magnify the effect of the HT without triggering it; (e) search methods for unused components during design-time verification, which thereafter can be removed as potentially suspicious [47]; and (f) Information Flow Tracking (IFT) methods that track the propagation of sensitive data and verify that they do not reach unauthorized sites in the design [11], [48], [49], [50], [51], [52]. In our case, IFT could be used to spot the connection between the register in the IP core where the information is stored and the preamble generation block in the DSP.…”

Section: Related Prevention and Detection De-fense Mechanismsmentioning

confidence: 99%

Leaking Wireless ICs via Hardware Trojan-Infected Synchronization

Diaz-Rizo¹,

Aboushady²,

Stratigopoulos³

2023

IEEE Trans. Dependable and Secure Comput.

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We propose a Hardware Trojan (HT) attack in wireless Integrated Circuits (ICs) that aims at leaking sensitive information within a legitimate transmission. The HT is hidden inside the transmitter modulating the sensitive information into the preamble of each transmitted frame which is used for the synchronization of the transmitter with the receiver. The data leakage does not affect synchronization and is imperceptible by the inconspicuous nominal receiver as it does not incur any performance penalty in the communication. A knowledgeable rogue receiver, however, can recover the data using signal processing that is too expensive and impractical to be used during run-time in nominal receivers. The HT mechanism is designed at circuit-level and is embedded entirely into the digital section of the RF transceiver having a tiny footprint. The proposed HT attack is demonstrated with measurements on a hardware platform. We demonstrate the stealthiness of the attack, i.e., its ability to evade defenses based on testing and run-time monitoring, and the robustness of the attack, i.e., the ability of the rogue receiver to recover the leaked information even under unfavorable channel conditions.

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“…The majority of IFA frameworks are designed to handle digital hardware. In contrast, the VeriCoq-IFT framework [6] introduces the capabilities to process mixed-signal designs when analyzing the information flow [7]. The analysis indicates whether sensitive information is leaked to the design's output signals.…”

Section: B Vericoq-iftmentioning

confidence: 99%

“…As stated in [7], for analog components, information is carried by voltage and current. Therefore, when setting the voltage at ae, the information can be read at both terminals of the memristor via the current.…”

Section: Related Workmentioning

confidence: 99%

Quantitative Information Flow for Hardware: Advancing the Attack Landscape

Reimann

Erdönmez

Šišejković

et al. 2023

2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

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Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computingin-memory (CIM). Various computer architectures have been proposed to integrate CIM blocks in their design, forming a mixed-signal system to combine the computational benefits of CIM with the robustness of conventional CMOS. Novel electronic design automation (EDA) tools are necessary to design and manufacture these so-called neuromorphic systems. Furthermore, EDA tools must consider the impact of security vulnerabilities, as hardware security attacks have increased in recent years. Existing information flow analysis (IFA) frameworks offer an automated tool-suite to uphold the confidentiality property for sensitive data during the design of hardware. However, currently available mixed-signal EDA tools are not capable of analyzing the information flow of neuromorphic systems. To illustrate the shortcomings, we develop information flow protocols for NVMs that can be easily integrated in the already existing tool-suites. We show the limitation of the state-of-the-art by analyzing the flow from sensitive signals through multiple memristive crossbar structures to potential untrusted components and outputs. Finally, we provide a thorough discussion of the merits and flaws of the mixed-signal IFA frameworks on neuromorphic systems.

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Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs

Cited by 8 publications

References 29 publications

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Leaking Wireless ICs via Hardware Trojan-Infected Synchronization

Quantitative Information Flow for Hardware: Advancing the Attack Landscape

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