Progress on carbon nanotube BEOL interconnects

Uhlig, Benjamin; Liang, Jie; Lee, J.; Ramos, R.; Dhavamani, Abitha; Nagy, Nicole; Dijon, Jean; Okuno, Hanako; Kalita, Dipankar; Georgiev, Vihar P.; Asenov, A.; Amoroso, Salvatore; Wang, L.; Millar, C.; Könemann, Fabian; Gotsmann, Bernd; Goncalves, G.; Chen, B.; Pandey, Reetu Raj; Chen, Rongmei; Todri‐Sanial, Aida

doi:10.23919/date.2018.8342144

Cited by 11 publications

(7 citation statements)

References 23 publications

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“…Due to strong SP2 bonding between carbon atoms, CNTs are much less susceptible to EM problems than copper interconnects and can carry high current densities [ 284 ]. Comprehensive reviews about carbon nanotube interconnects are presented respectively by Uhlig [ 285 ] and Santos [ 286 ], and reviews include the following information: (1) Process and growth of carbon nanotube interconnects compatible with back-end-of-line integration, (2) modeling and simulation from atomistic to circuit-level benchmarking and performance prediction, (3) characterization and electrical measurements, and (4) previous research work on single-wall, multi-wall carbon nanotubes (MWCNT) and composite of copper and SWCNT (Cu-SWCNT). Carbon nanotubes, more specifically MWCNTs, have been identified as potential alternatives to diminish copper interconnect scaling issues [ 286 ].…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

“…Carbon nanotubes, more specifically MWCNTs, have been identified as potential alternatives to diminish copper interconnect scaling issues [ 286 ]. However, using CNTs as interconnect material in semiconductor manufacturing is a huge paradigm shift, even higher than the change from aluminum (Al) to copper (Cu) in backend of line metallization [ 285 ]. Therefore, a lot of research efforts are still needed to realize the interconnection of carbon nanotubes.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Metal Materials Interconnectmentioning

confidence: 99%

Section: Metal Materials Interconnectmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…Without loss of generality, we assume our LC scheme to be based on the use of Mg/MgO vias for obfuscating the vertical interconnects of the 3D IC. Emerging interconnects such as those based on carbon nanotubes [41] may become relevant in the future as well.…”

Section: Untrusted Foundriesmentioning

confidence: 99%

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during and after manufacturing. While both techniques enable protecting the intellectual property (IP) of ICs, SM can further mitigate the insertion of hardware Trojans (HTs). In this paper, we strive for the "best of both worlds," that is we seek to combine the individual strengths of SM and LC. By jointly extending SM and LC techniques toward 3D integration, an up-and-coming paradigm based on stacking and interconnecting of multiple chips, we establish a modern approach to hardware security. Toward that end, we develop a security-driven CAD and manufacturing flow for 3D ICs in two variations, one for IP protection and one for HT prevention. Essential concepts of that flow are (i) "3D splitting" of the netlist to protect, (ii) obfuscation of the vertical interconnects (i.e., the wiring between stacked chips), and (iii) for HT prevention, a security-driven synthesis stage. We conduct comprehensive experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores designs (and others). Strengthened by extensive security analysis for both IP protection and HT prevention, we argue that entering the third dimension is eminent for effective and efficient hardware security.

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“…Experimental work has demonstrated that both metallic SWCNT [8] and metallic MWCNT [9] are good candidates of high-performance circuit interconnects that can operate more than 1 GHz frequency. In addition, doping techniques, such as NO 2 , H 2 SO 4 , SOCL 2 , PtCl 4 , etc., [10]- [15] have been experimentally found to be effective in significantly improving the conductance of CNT interconnects. We use the CNT interconnect models based on compact models proposed in [16] and [17].…”

Section: Introductionmentioning

confidence: 99%

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Chen

Lin

Liang

et al. 2022

IEEE Trans. VLSI Syst.

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The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of 0.28×,0.52×, and 0.76× respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.This work was supported in part by the European Commission H2020 CONNECT Project under Agreement 688612 (http://www.connect-h2020.eu/) and in part by the Marie Skłodowska-Curie Individual Fellowship under Grant 894805 (H-3D-SOC).

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Progress on carbon nanotube BEOL interconnects

Cited by 11 publications

References 23 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

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