Progress of STT-MRAM technology and the effect on normally-off computing systems

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

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“…This paper reports our efforts to attain normally off computers and discusses the challenges that remain. 4,14,15 …”

Section: Introductionmentioning

confidence: 99%

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

Ando¹,

Fujita²,

Ito³

et al. 2014

Journal of Applied Physics

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110

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“…It is easy to identify that the initial energy of STT-MRAM is currently higher than SRAM. However, with the evolution in materials and MTJ manufacturing process, it is expected that the initial dynamic power consumption will decrease to the point where STT-MRAM becomes comparable or even better than SRAM [4,5]. However, for bank sizes larger than 8 MB, the observation is that by increasing the memory bank size, the write dynamic energy of SRAM will become equal to or higher than STT-MRAM at some point.…”

Section: Stt-mram Srammentioning

confidence: 76%

Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

Cargnini

Torres

Brum

et al. 2014

JLPEA

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Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM. We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

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“…This is represented by the small value of the exponent k = 0.1 in the second line of Eqs. (9) and (10). Thus σ u B is mostly constant for m < 0 and m > 0, but a jump in its value is introduced at m ≈ 0.…”

Section: A General Discussionmentioning

confidence: 95%

“…Recently, this interest has shifted to PMA spin valves and magnetic tunnel junctions (MTJs) due to their potential in reducing the switching energy while preserving thermal stability in spin-torque transfer (STT) magnetic random access memory (MRAM) applications [5][6][7][8][9][10]. These devices could improve current CMOS processor cache technology by lowering power consumption at sub-20-nm nodes [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Variable variance Preisach model for multilayers with perpendicular magnetic anisotropy

et al. 2016

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We present a variable variance Preisach model that fully accounts for the different magnetization processes of a multilayer structure with perpendicular magnetic anisotropy by adjusting the evolution of the interaction variance as the magnetization changes. We successfully compare in a quantitative manner the results obtained with this model to experimental hysteresis loops of several [CoFeB/Pd] n multilayers. The effect of the number of repetitions and the thicknesses of the CoFeB and Pd layers on the magnetization reversal of the multilayer structure is studied, and it is found that many of the observed phenomena can be attributed to an increase of the magnetostatic interactions and subsequent decrease of the size of the magnetic domains. Increasing the CoFeB thickness leads to the disappearance of the perpendicular anisotropy, and such a minimum thickness of the Pd layer is necessary to achieve an out-of-plane magnetization.

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Progress of STT-MRAM technology and the effect on normally-off computing systems

Cited by 89 publications

References 4 publications

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

Variable variance Preisach model for multilayers with perpendicular magnetic anisotropy

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