Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

Abstract

Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM. We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

New Content Addressable Memory Architecture for Multi-Core Applications

“…The tested DPCAM has a lower read latency than the tested SA cache; this is because DPCAM compares the incoming tag directly with the stored tag, whereas SA caches must use an index to access the location with a tag to compare to, which increases the latency. Generally, a cache memory based on AM has a latency of around 2 ns for 64 KiB [20], 1.66 ns for AM with 1KiB, and 1.69 ns for 4-way set associative with 2 KiB, which is used in cache controllers [21]. However, the write latency for a cache memory based on AM typically exceeds 2 ns for 64KiB [20].…”

Dual-Port Content Addressable Memory for Cache Memory Applications

“…Whereas in DPCAM, the incoming tag is directly compared with the stored tag. Usually, the cache memory based on AM has around 2 ns read latency with the 64 KiB [27], 1.66 ns in AM with 1KiB, and 1.69 ns in 4-way set associative with 2 KiB which is used in cache controller [14]. But write latency for the cache memory based on AM usually exceeds 2 ns for 64KiB [27].…”

Development and Research of a Theoretical Model of the Magnetic Tunnel Junction

“…Spin-tunnel magnetoresistive nanostructures are used in various spintronic devices: in magnetic field sensors [ 1 , 2 , 3 , 4 ], in magnetoresistive biosensors [ 5 ], and in magnetoresistive memory elements [ 6 , 7 , 8 ]. The magnetic tunnel junction (MTJ) consists of a conducting free magnetic layer (FL), a dielectric tunnel barrier, and a conducting fixed magnetic layer (FixL) [ 7 , 8 ].…”