Progress in autonomous fault recovery of field programmable gate arrays

Parris, Matthew; Sharma, Carthik A.; DeMara, Ronald F.

doi:10.1145/1978802.1978810

Cited by 31 publications

(23 citation statements)

References 26 publications

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“…Fault recovery mechanisms in FPGAs can be classified in offline and online methods [9]. The former imply stopping the data processing while the healing process is active, while the latter involve being able to keep processing data while the system is faulty or being repaired, with the advantage of keeping the system running and therefore increasing the system's availability.…”

Section: Analysis Of the State Of The Artmentioning

confidence: 99%

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

Gallego¹,

Mora²,

Otero³

et al. 2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

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Section: Analysis Of the State Of The Artmentioning

confidence: 99%

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

Gallego¹,

Mora²,

Otero³

et al. 2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

View full text Add to dashboard Cite

show abstract

“…Previous works establish the successful use of Evolutionary Algorithms for adaptive self-recovery of hardware systems based on reconfigurable logic, especially FPGAs [12], [13], [25], [26] and [23]. In [12], a survey of techniques ranging from passive to dynamic in classification are presented to tackle hard faults in SRAM-based FPGAs for small circuit case studies.…”

Section: A Genetic Algorithm-based Refurbishment Of Reconfigurable Hmentioning

confidence: 99%

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Ashraf

DeMara

2013

IEEE Trans. Comput.

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In this work, Field Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist Driven Evolutionary Refurbishment (NDER) technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1% in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations.Successful refurbishment of the apex4 circuit having a total of 1252 LUTs with 10% spares is achieved in as few as 633 generations on average when subjected to simulated randomly-injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

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“…Of particular note are present-day field programmable gate array (FPGA) devices that contain large quantities of embedded static RAM (SRAM) where there is a growing interest in 'design for reliability' strategies that encompass functional diversity, modular redundancy, fine-grained fault-tolerant design and autonomous self-repair. 9 New design approaches are needed for custom logic, for which data error detection and correction (EDC) strategies such as two-dimensional hamming codes or fault-tolerant logic are typically applied. Figure 1 illustrates three examples of fine-grained logic redundancy strategies that have been proposed.…”

Section: Introductionmentioning

confidence: 99%

Creating self-configuring logic with built-in resilience to multiple-upset events

McWilliam

Schiefer

Purvis

2015

Proceedings of the Institution of Mechanical Engineers, Part B:

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Electronic systems are prone to failures, whether during manufacture or throughout their in-service lifetime. A number of design and fabrication techniques are presently employed that maintain an economical production yield. However, the cost of through-life maintenance and fault mitigation operations for complex, high-value systems remains a major challenge and requires new design methods in order to increase their resilience. In this article, the focus is on applications that are sensitive to transient random errors caused by single-event upsets and multiple-bit upsets occurring within their electronic systems and sub-systems, as well as applications that benefit from fault detection and localisation. A novel self-restoration strategy is proposed based on a two-layer design approach comprising a fault-tolerant coordination layer with convergent cellular automata and a configurable functional logic layer. This design strategy is able to self-reconstruct the correct functional logic configuration in the event of transient faults without external intervention. The necessary convergent cellular automata rule set and state table sizes for 3 3 3 and 4 3 4 binary coded patterns are analysed in order to estimate the generic resource requirements for larger designs. Additionally, the possibility of exploiting the design for built-in fault detection and diagnostic reporting is investigated.

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Progress in autonomous fault recovery of field programmable gate arrays

Cited by 31 publications

References 26 publications

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Creating self-configuring logic with built-in resilience to multiple-upset events

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