Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Abstract

In this work, Field Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist Driven Evolutionary Refurbishment (NDER) technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1% in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations.Successful refurbishment of the apex4 circuit having a total of 1252 LUTs with 10% spares is achieved in as few as 633 generations on average when subjected to simulated randomly-injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

Placement Strategies for Faulty Cells in Module Relocation Based BISR Approach

“…The shifting is very time consuming as it requires that much more number of reconfigurations. A self-repairing algorithm which acts on the configuration of selected LUTs inside the FPGA is discussed in [9]; based on the faulty condition, LUT-level repairing is done by mutation and cross-over process. A novel approach for FPGA self-repair systems using dynamic partial reconfiguration called reconfigurable adaptive redundancy systems is discussed in [10].…”

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks

“…Namley, a tractable in-field reconfiguration-based approach is developed to leverage in-field configurability to mitigate the impact of process variation. Reconfigurable fabrics are characterized by their fabric flexibility, which allows realization of logic elements at medium and fine granularities, as well as in-field adaptability, which can be leveraged to realize variation tolerance and fault resiliency as widely-demonstrated for CMOSbased approaches such as [5], [6]. Utilizing reconfigurable computing by applying hardware and time redundancy to the digital circuits offers promising and robust techniques for addressing the above-mentioned reliability challenges.…”

“…Utilizing reconfigurable computing by applying hardware and time redundancy to the digital circuits offers promising and robust techniques for addressing the above-mentioned reliability challenges. For instance, it is shown in [6] that a successful refurbishment for a circuit with 1,252 look-up tables (LUTs) can be achieved with only 10% spare resources to accommodate both soft and hard faults.…”

Handbook of Research on Natural Computing for Optimization Problems

“…The authors of , Koonar (2003Koonar ( ,2005, Scott (1994), , Shackleford (2001), Aporntewan and Chongstitvatana (2001), Tang and Leslie (2004), Vavouras, Papadimitriou and Papaefstathiou (2009, July), Chen et al (2008), Fernando et al (2010), Kok et al (2013), Nambiar, Balakrishnan, Khalil-Hani, and Marsono (2013), Ashraf, and DeMara (2013) and a number of researchers indicated regarding the hardware implementation of GA. Most of the works in this field have targeted the development of fast GA hardware that outperforms the software GAs in speed.…”