Process Induced Stresses in Cavity SOI Wafers

Abstract

Silicon-on-insulator wafers with buried cavities have been utilized in recent applications ranging from MEMS based resonator devices to double gate MOS devices. The objective of this study is to determine whether the magnitude and orientation of residual stress concentrations generated by the etched silicon cavities, which can introduce reliability issues for these devices, particularly if a large tensile stress results from this processing. The results of this study show that the residual stress state of the bonded wafers may be tensile or compressive and the magnitude and orientation of these stresses depend on both the etched cavity geometry and the oxidation process, which can be verified in the development phase with an infrared polariscope. There is evidence that the stress in the handle wafer prior to bonding is maintained even after high temperature annealing and wafer thinning. Thus, residual stresses may be controllable prior to bonding.