In order to achieve a better understanding of the behaviour of copper in p-type silicon, studies of the recombination of copper were carried out by the microwave photoconductive decay measurement method (µPCD) using high-intensity bias light. It was observed that in the presence of small oxygen precipitates, high-intensity light could be used to activate precipitation of interstitial copper. It is suggested that high-intensity light changes the charge state of interstitial copper from positive to neutral, which enhances the precipitation. The precipitation follows Ham's kinetics and results in an increase in the recombination rate, which is detectable even with very low copper concentrations. This phenomenon can be used to detect low levels of copper contamination by the µPCD method. In addition, it was observed that out-diffusion as well as in-diffusion of interstitial copper could be affected by an external corona charge. Thus, it is suggested that copper atoms do not form stable bonds at the Si-SiO 2 interface after out-diffusion from bulk silicon.
We have studied internal gettering efficiency of iron in silicon by Deep Level Transient Spectroscopy (DLTS) and standard lifetime-methods (SPV, PCD). Conventional high-low-high anneals were performed to produce a series of wafers with varying denuded zone (DZ) width and oxygen precipitation density. The wafers were intentionally iron contaminated to a level of about 3-5 * 10 13 cm −3. After contamination the wafers were annealed at 900 • C and then slowly cooled to 850, 800, 750, 700 or 600 • C. After cooling the remaining interstitial iron concentration was measured by SPV,-PCD and DLTS. The experimental results are compared with simulations. Our results indicate that with this contamination level, the gettering is effective only at temperatures below 750 • C when iron is supersaturated over a factor of twenty. For temperatures above 750 • C the gettering is limited by iron precipitation in the bulk.
SOI wafers with buried cavities can be used in MEMS fabrication to give more freedom in design and to simplify the process. Sometimes an etch stop layer is needed when DRIE is used to release the MEMS structures in order to prevent etching from continuing at the bottom of the cavity. Thermal oxidation of the cavity wafer as a method for forming an etch stop layer was studied. It was found that oxidation parameters such as temperature and thickness affect the formation of dislocations which in turn may cause voids in bonding. Higher oxidation temperature and thicker oxide were found to yield better bonding results. Patterns and geometry of etched features also play a role.
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