Process characterisation with dynamic test structures

Coll, Philippe; Robert, Michel; Regnier, X.; Auvergne, D.

doi:10.1049/el:19931175

Cited by 7 publications

(5 citation statements)

References 3 publications

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“…For the current expressions we use the standard Shichman and Hodges model, which appears to be sufficient for average calculations, short channel effects being later introduced through calibration coefficients on the effective mobility length ratio as discussed in [16]. After some tedious but not complicated calculations, equ.…”

Section: Short Circuit Power Evaluationmentioning

confidence: 99%

Explicit evaluation of short circuit power dissipation for CMOS logic structures

Turgis

Azémard

Auvergne

1995

Proceedings of the 1995 International Symposium on Low Power Design - ISLPED '95

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For supply voltage standards such as Vdd > V TN + |V TP | short-circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short-circuit power dissipation, Psc, in CMOS structures. A first order calculation results in an explicit formulation for Psc, which clearly shows up the design and load parameters. Validations are performed on different configurations of inverters by comparison with HSPICE simulations. Discussions on the relative importance of short-circuit and dynamic power dissipation is given, together with considerations allowing an easy extension to gates.

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Section: Short Circuit Power Evaluationmentioning

confidence: 99%

Explicit evaluation of short circuit power dissipation for CMOS logic structures

Turgis

Azémard

Auvergne

1995

Proceedings of the 1995 International Symposium on Low Power Design - ISLPED '95

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“…2), represent speed characteristic parameters of the considered process, and are defined through average values of mobilities and transistor lengths across the full voltage excursion. Their values can be extracted directly from the characterization of specific oscillators or calibrated from simulation of inverters [20].…”

Section: Inv1 Inv2mentioning

confidence: 99%

Design and selection of buffers for minimum power-delay product

Turgis

Azémard

Auvergne

Proceedings ED&TC European Design and Test Conference

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Using explicit modeling of delays we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to standard cell library in comparing implementations for different selection alternatives.

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“…15), µ eff (equ. 7,8)and τ st and R(µ) (equ. 6), is quite good and validates the low voltage corrections proposed here.…”

Section: Low Voltage Input Slope Effectsmentioning

confidence: 99%

“…µ eff correspond to the average effective mobility over the voltage swing, including saturation effects. As shown in [8], these parameters can be obtained directly from calibrations on SPICE simulations (using foundry supplied level 6 model, for ex.) or determined directly from specific test structures implemented on ring oscillators.…”

Section: Low Voltage Modelling Of Step Responsesmentioning

confidence: 99%