Process and Device Performance of Submicrometer-Channel CMOS Devices Using Deep-Trench Isolation and Self-Aligned TiSi/sub 2/ Technologies

Yamaguchi, T.; Morimoto, S.; Park, Hee Kyun; Eiden, Gregory C.

doi:10.1109/jssc.1985.1052282

Cited by 9 publications

(2 citation statements)

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“…where N is the total flux of all neutral gas species (cm - At steady state r~p,ttering = ? 'deposition, from which 4,0 can be determined 4,0 = Ni" fJ(Xc " N -fc + Ni " fs) [3] Surface blocking is considered to affect only the polysilicon surface; the oxygen released from the etching SOG film helps to prevent carbon-containing contamination (13) on that surface. This means that fc ~ 0 and therefore 4,o ~ 1 for the oxide surface.…”

Section: Discussionmentioning

confidence: 99%

“…Deposition of thick (>4000 A) polysilicon into high aspect ratio openings, followed by etchback planarization to smooth the resultant topography, has seen applications in trenches used for isolation, capacitors, and topside substrate contacts (1)(2)(3)(4). In addition, the same basic scheme has recently been used to create emitter contacts for high performance bipolar and BICMOS applications.…”

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confidence: 99%

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Polysilicon Planarization Using Spin‐On Glass

Ramaswami

Nagy

1992

J. Electrochem. Soc.

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A process to planarize thick (>4000 A) polysilicon deposited into high aspect ratio openings using spin-on glass (SOG) as the planarizing material is described. The process uses NF3 + CHF3 + O2 in a commercially available batch reactive ion etching system, and has been optimized to etch polysilicon and SOG at the same rate. The mechanism of the etch is explored through the use of a physical model.

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Section: Discussionmentioning

confidence: 99%

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confidence: 99%