Process and Characteristics of Fully Silicided Source/Drain (FSD) Thin-Film Transistors

Lin, Chiung–Wei; Hsiao, Yi‐Hsuan; Tsui, Bing‐Yue

doi:10.1109/ted.2006.885651

Cited by 42 publications

(9 citation statements)

References 35 publications

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“…Low-temperature crystallization processes of the poly-Si channel films have been studied extensively, including solid-phase crystallization (SPC), laser crystallization (LC) and metal-induced lateral crystallization (MILC) 14–16 . The MILC method has a metal contamination issue in the poly-Si channel, resulting in the degradation of the junction leakage.…”

Section: Resultsmentioning

confidence: 99%

“…4(a) . The high-intensity laser beam causes the nearly complete melting (also denoted as partial melting) and a small amount of residual unmolten Si acts as a liquid/solid interface crystal seed, permitting controlled growth upward from the interface with the molten Si 14 . The tight control of the laser flux at 320 mJ/cm 2 was found to precisely achieve the epitaxial-like (e-like) Si with the best crystallization from a-Si.…”

Section: Resultsmentioning

confidence: 99%

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High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

Huang

Yang

et al. 2017

Sci Rep

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Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

Huang

Yang

et al. 2017

Sci Rep

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“…Moreover, metal-oxide NC flash memory using hafnium oxide NCs embedded in a SiO 2 matrix reportedly exhibits good retention and endurance and a large memory window. In comparison with their metal NC counterparts, metal-oxide NC memory has advantages such as compatibility with complementary metal-oxidesemiconductor technology, rapid fabrication, and high trap densities [8,9]. The structure of NCs embedded in a dielectric matrix has been controlled using various methods, such as sputtering followed by annealing [10], ion implantation [11], and self-assembly [12].…”

Section: Introductionmentioning

confidence: 99%

Tunable bandgap energy of fluorinated nanocrystals for flash memory applications produced by low-damage plasma treatment

Huang¹,

Lin²,

Wang³

et al. 2012

Nanotechnology

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A plasma system with a complementary filter to shield samples from damage during tetrafluoromethane (CF(4)) plasma treatment was proposed in order to incorporate fluorine atoms into gadolinium oxide nanocrystals (Gd(2)O(3)-NCs) for flash memory applications. X-ray photoelectron spectroscopy confirmed that fluorine atoms were successfully introduced into the Gd(2)O(3)-NCs despite the use of a filter in the plasma-enhanced chemical vapour deposition system to shield against several potentially damaging species. The number of incorporated fluorine atoms can be controlled by varying the treatment time. The optimized memory window of the resulting flash memory devices was twice that of devices treated by a filterless system because more fluorine atoms were incorporated into the Gd(2)O(3)-NCs film with very little damage. This enlarged the bandgap energy from 5.48 to 6.83 eV, as observed by ultraviolet absorption measurements. This bandgap expansion can provide a large built-in electric field that allows more charges to be stored in the Gd(2)O(3)-NCs. The maximum improvement in the retention characteristic was >60%. Because plasma damage during treatment is minimal, maximum fluorination can be achieved. The concept of simply adding a filter to a plasma system to prevent plasma damage exhibits great promise for functionalization or modification of nanomaterials for advanced nanoelectronics while introducing minimal defects.

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“…Both source and substrate terminals were biased at 0 V. The "V t shift" is defined as the threshold voltage change of a device between the programmed and the erased states. 21 Figure 4 shows the four-level threshold voltage (V th ) distribution of multilevel programming wherein a sharp V th distribution can achieve reliable operation. The devices were programmed with a 3 V memory window and erased.…”

Section: Resultsmentioning

confidence: 99%

Two-bit/four-level Pr2O3 trapping layer for silicon-oxide-nitride-oxide-silicon-type flash memory

Lin

You

Chien

2011

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Articles you may be interested inSilicon-oxide-high-κ -oxide-silicon memory using a high-κ Y 2 O 3 nanocrystal film for flash memory application Annealing temperature effect on the performance of nonvolatile HfO 2 Si-oxide-nitride-oxide-silicon-type flash memory J.This study proposes and demonstrates a silicon-oxide-nitride-oxide-silicon (SONOS)-type memory device based on a high-k dielectric praseodymium oxide (Pr 2 O 3 ) trapping layer. In the proposed design, channel hot electron injection programming and band-to-band hot-hole injection erasing allow highly efficient two-bit and four-level device operation. The proposed design also has a total memory window of 5 V, a ten-year V t retention window larger than 0.8 V between adjacent levels, and enough memory window for 10 5 programming/erasing cycles of endurance. The proposed SONOS-type Pr 2 O 3 trapping layer flash memory exhibits large memory windows, high program/ erase speed, good endurance, and good disturbance characteristics.

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Process and Characteristics of Fully Silicided Source/Drain (FSD) Thin-Film Transistors

Cited by 42 publications

References 35 publications

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

Tunable bandgap energy of fluorinated nanocrystals for flash memory applications produced by low-damage plasma treatment

Two-bit/four-level Pr2O3 trapping layer for silicon-oxide-nitride-oxide-silicon-type flash memory

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