Electronic displays and flexible electronics are poised to significantly impact emerging industries, including displays, energy products, sensors and medical devices, building a market that will significantly grow in the future. The implementation of transparent electronic devices requires the use of material components that could be formed using controlled deposition in the appropriate orientation onto a transparent flexible substrate. Here, we report a simple and efficient means of depositing onto a flexible polyimide (PI) substrate a highly ordered and highly aligned zinc oxide (ZnO) film for use as a carrier transporting and semiconducting layer with controlled surface charge density for thin-film transistor (TFT) applications.The deposition approach is based on the solution-coating of a zinc-acetate suspension under controlled conditions of the spread flow rate, droplet size of the drops, speed limit, and the oxygen (ca. O 2 ) plasma treatment of the coated film surface on the PI substrate. The plasma surface interactions on the surface states of the ZnO films for various times (ca. 1-5 min) were studied using X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy. Moreover, the effects of O 2 plasma and the subsequent thermal annealing in an O 2 atmosphere at 250 C on the properties of ZnO films were studied for its efficacy in TFT applications in terms of the charge carrier density and the change in the mobility. ZnO thin-film-based TFTs on PI exhibited a very high electron mobility of 22.8 cm 2 V À1 s À1 at a drain bias of 5 V after treatment with O 2 plasma for 2 min. Furthermore, the plasma treatment for long durations of time caused a reduction in the charge carrier density from 1.58 Â 10 19 cm À3 for the 2 min treatment to 1.13 Â 10 17 cm À3 for the 5 min treatment, and the corresponding electron mobility was changed from 22.8 and 3.1 cm 2 V À1 s À1 for the treatment times of 2 min and 5 min, respectively. The spin-coating technique used to deposit very thin ZnO films is currently used in microelectronics technology, which helps to ensure that the described ZnO thin-film deposition approach can be implemented in production lines with minimal changes in the fabrication design and in the auxiliary tools used in flexible electronics production.
We have developed a simple method for the preparation of ZrO 2 ultrathin films; it involves a sequence of ZrCl 4 precursor preparation in an ice bath, sol-gel spin-coating processing, baking, and annealing. The film thickness was controllable and tunable by altering the ZrCl 4 /hexanol ratio. High-resolution transmission electron microscopy ͑TEM͒ and thermal desorption spectrometry indicated that the fabricated ultrathin film was thermally stable at annealing temperatures as high as 900°C. Diffraction patterns of TEM indicated that the films obtained at various annealing temperatures were amorphous. Electron spectroscopy for chemical analysis ͑ESCA͒ demonstrated an increase in the intensity of the signal for the Zr-O bonds upon increasing the annealing temperature, whereas those for the signals of carbon and chlorine decreased. The ESCA and TEM analyses also suggested that the thickness of the silicon dioxide film increased upon increasing the annealing temperature. The electrical properties, such as the breakdown field ͑12.5 MV/cm͒ and the gate current density ͑Ͻ10 −7 A/cm 2 ͒, of the sol-gel-derived ZrO 2 ultrathin films obtained after annealing at 900°C suggested that they were good electrical insulators. These ZrO 2 thin films are expected to behave as capacitors and as coatings for insulating films.
In this paper, we propose a method for depositing the charge trapping layer of a high-k polySi-SiO 2 -ZrO 2 -SiO 2 -Si ͑SOZOS͒ memory device. In this approach, the trapping layer was formed through simple two steps: ͑i͒ spin-coating of the ZrCl 4 precursor and ͑ii͒ rapid thermal annealing for 1 min at 900°C under an oxygen atmosphere. The morphology of the ZrO 2 charge trapping layer was confirmed through X-ray photoemission spectroscopy analysis. The sol-gel-derived layer exhibited improved charge trapping in the SOZOS memory device, resulting in a threshold voltage shift of 2.7 V in the I d -V g curve, P/E ͑program/erase͒ speeds as fast as 0.1 ms, good data retention up to 10 4 s ͑only a 5% charge loss due to deep trapping in the ZrO 2 layer͒, and good endurance ͑no memory window narrowing after 10 5 P/E cycles͒.The first floating-gate ͑FG͒ nonvolatile semiconductor memory was invented by Sze and Kahng in 1967. 1 Conventional FG memory uses polysilicon as a charge-storage layer surrounded by the dielectric. 2 Although floating-gate structures can achieve high densities and good program/erase ͑P/E͒ speeds and exhibit good reliability in portable flash memory devices, there are concerns regarding the ability to scale up their production. 3 When the tunneling oxide thickness is below 10 nm, the storage charge in the FG leaks readily because defects form in the tunneling oxide after repeated write-erase cycles or through direct tunneling of the current.PolySi-oxide-nitride-oxide-silicon ͑SONOS͒ memory devices have been studied recently as an approach to solving the issue of scaling FG memory. 3 Because of their spatially isolated deep-level traps, SONOS memories exhibit better charge retention than do FG memories that have a bitcell tunneling oxide layer thinner than 10 nm. As a result, a single defect in the tunneling oxide will not cause the discharge of the memory cell. 3 SONOS memory devices use silicon nitride as a charge trapping layer; the conduction band offset between the tunneling oxide and nitride is 1.05 eV. When a positive voltage is applied on the gate, the band bends downward so that the electrons in the Si subconduction band will tunnel through the tunneling oxide and a portion of the nitride will become trapped in the charge trapping layer. Before they become trapped in the nitride, the electrons must tunnel through a portion of the nitride, which degrades the program speed. In addition, because the conduction band offset of the nitride is only 1.05 eV, back tunneling of the trapped electron may also occur. To solve these problems, high-k materials are potential candidates to replace the traditional silicon nitride as the charge trapping layer.The advantages of using high-k materials are the larger band offset with the tunneling oxide and the greater number of trapping sites than those found in silicon nitride. For an HfO 2 high-k material, the conduction band offset between the tunneling oxide and HfO 2 is 1.6 eV. When programming, the electron will tunnel through a shorter distance in HfO 2 than ...
We have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride. This new structure exhibits excellent characteristics in terms of larger memory windows and longer retention time compared to control devices. Using the same thickness 2.5 nm of the bottom tunneling oxide, we found that N 2 O is better than O 2 oxide. Retention property is improved when the thickness of N 2 O is increased to 3.0 nm.
This paper presents a technique involving a sol-gel deposition method applied to the deposition of zinc oxide thin film for a transistor as a semiconductor layer. This method was used for manufacturing the essential thin films of II-VI semiconductors. Zinc oxide (ZnO) bottom-gate (BG) thin-film transistors (TFTs) have been successfully fabricated at low temperatures. We investigated the electrical characteristics of ZnO thin-film transistors at various concentrations of ZnO solution: 0.02 M, 0.03 M, 0.04 M, and 0.05 M. All of the ZnO films exhibited a hexagonal wurtzite polycrystalline structure with (002) preferred orientation. Atomic force microscopy (AFM) revealed the formation of grains or clusters as a result of the accumulation of nanoparticles, and the grain size increased with increasing solution concentration. The coated ZnO films were employed as the active channel layer in thin-film transistors, and the impact of the solution concentration on the device performance was examined. As the solution concentration was increased, the field-effect mobility increased from 1 × 10-4 cm 2 /V-s to 1.2 × 10-1 cm 2 /V-s, the threshold voltage increased from 4.8 V to 11.1 V, and the I on /I off ratio increased from 10 4 to 10 6. The on-off ratio (I on / off) was found to be 10 6. The 0.05 M ZnO solution performed optimally.
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