Abstract:The bipolar resistive switching (BRS) between a metallic low resistance state (LRS) and an insulating high resistance state (HRS) is demonstrated for annealed graphene oxide (GO) thin film-based device structures with aluminum (Al) as one of the contact electrodes. An optimal switching of ∼10 order is recorded for Al/GO (200 °C)/indium tin oxide (ITO) among the device structures in metal (M)/GO (T)/metal (M) configurations (M = Al, Au, or ITO and M = Au or Al), fabricated using GO (T)/metal (M), annealed at di… Show more
“…Table compares the power consumption of our device and previous reported GO-based resistive memory devices. It is noteworthy that the device in this work has the lowest set power. ,,− …”
Suppressing
the operating current in resistive memory devices is
an effective strategy to minimize their power consumption. Herein,
we present an intrinsic low-current memory based on two-dimensional
(2D) hybrid heterostructures consisting of partly reduced graphene
oxide (p-rGO) and conjugated microporous polymer (CMP) with the merits
of being solution-processed, large-scale, and well patterned. The
device with the heterostructure of p-rGO/CMP sandwiched between highly
reduced graphene oxide (h-rGO) and aluminum electrodes exhibited rewritable
and nonvolatile memory behavior with an ultralow operating current
(∼1 μA) and efficient power consumption (∼2.9
μW). Moreover, the on/off current ratio is over 103, and the retention time is up to 8 × 103 s, indicating
the low misreading rate and high stability of data storage. So far,
the value of power is about 10 times lower than those of the previous
GO-based memories. The bilayer architecture provides a promising approach
to construct intrinsic low-power resistive memory devices.
“…Table compares the power consumption of our device and previous reported GO-based resistive memory devices. It is noteworthy that the device in this work has the lowest set power. ,,− …”
Suppressing
the operating current in resistive memory devices is
an effective strategy to minimize their power consumption. Herein,
we present an intrinsic low-current memory based on two-dimensional
(2D) hybrid heterostructures consisting of partly reduced graphene
oxide (p-rGO) and conjugated microporous polymer (CMP) with the merits
of being solution-processed, large-scale, and well patterned. The
device with the heterostructure of p-rGO/CMP sandwiched between highly
reduced graphene oxide (h-rGO) and aluminum electrodes exhibited rewritable
and nonvolatile memory behavior with an ultralow operating current
(∼1 μA) and efficient power consumption (∼2.9
μW). Moreover, the on/off current ratio is over 103, and the retention time is up to 8 × 103 s, indicating
the low misreading rate and high stability of data storage. So far,
the value of power is about 10 times lower than those of the previous
GO-based memories. The bilayer architecture provides a promising approach
to construct intrinsic low-power resistive memory devices.
“…However, their high‐resistance state (HRS) to low‐resistance state (LRS) ratios (ON/OFF ratios) reported in the literature are lower than 10 4 . [ 12–14 ] This limits their use in large‐capacity and low‐power‐consumption storage, which is urgently needed with the development of the Internet of things and big‐data processing. Metal halide perovskites are proven to have high photoelectric and flexible properties, [ 15 ] which enable them good candidates for photoelectric dual‐control RRAM devices with low power consumption and secure data storage.…”
Perovskite resistive random-access memory (RRAM) is a promising candidate for next-generation logic, adaptive and nonvolatile memory devices, because of its high ON/OFF ratio, low-cost fabrication, and good photoelectric regulation performance. In this work, a flexible transparent CsPbBr 3 quantum dots (QDs) mixed in graphene oxide (GO) RRAM device is introduced, which is controllable by both an electric field and illumination. Under illumination, the ON/OFF ratio of the Ag/CsPbBr 3 QDs:GO/ITO device is ≈1.4 × 10 7 , which is 1077 times larger than that in the dark condition (1.3 × 10 4 ). The SET/RESET voltages are +2.28/−2.04 V and +1.68/−1.08 V under the dark and illumination conditions, respectively. As a flexible memory device, the resistances are little affected by the bending curvatures and load-cycling. Before and after 10 4 bending cycles with a radius of 5 mm under illumination, the ON/OFF ratios keep in the same order, which are 2.5 × 10 7 and 2.3 × 10 7 , respectively. The ratio values are 8.8 × 10 4 and 2.9 × 10 4 under the dark condition, respectively. This innovative resistive memory based on the CsPbBr 3 QDs:GO hybrid film supports a huge space for the development of photoelectrical dual-controlled flexible RRAM devices.
“…And the resistance of the rGO electrode is decreased by reducing the oxygen vacancy concentration, inducing the reset and transition back to the HRS. Electrical pulses can cyclically induce an HRS to LRS transition [56]. The realization of ultra-low energy consumption is also of great significance to the development of NC systems.…”
A memristor is a promising candidate of new electronic synaptic devices for neuromorphic computing. However, conventional memristors often exhibit complex device structures, cumbersome manufacturing processes, and high energy consumption. Graphene-based materials show great potential as the building materials of memristors. With direct laser writing technology, this paper proposes a lateral memristor with reduced graphene oxide (rGO) and Pt as electrodes and graphene oxide (GO) as function material. This Pt/GO/rGO memristor with a facile lateral structure can be easily fabricated and demonstrates an ultra-low energy consumption of 200 nW. Typical synaptic behaviors are successfully emulated. Meanwhile, the Pt/GO/rGO memristor array is applied in the reservoir computing network, performing the digital recognition with a high accuracy of 95.74%. This work provides a simple and low-cost preparation method for the massive production of artificial synapses with low energy consumption, which will greatly facilitate the development of neural network computing hardware platforms.
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