Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems

Pionteck, Thilo; Osterloh, Christoph

doi:10.1109/hpcsim.2013.6641419

Cited by 3 publications

(1 citation statement)

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“…This is especially true when simulating router architectures, that are capable to analyze the characteristics of data streams and show different behavior for different kind of traffics. For example, routers that are capable to detect and prioritize semi-static data streams such as proposed in [15] can only be tested when applying traffic patterns of applications in which semi-static data streams exist. These data streams are characterized by a number of consecutive packets following the same path for a longer period of time.…”

Section: Requirementsmentioning

confidence: 99%

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling

Joseph

Pionteck

2014

2014 International Symposium on System-on-Chip (SoC)

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This papers presents the design of a Network-on Chip (NoC) simulator for design space exploration of router ar chitectures. The simulator supports cycle-accurate router models and in addition allows the simulation of router architectures, which can adjust their processing according to the traffic type. Realistic traffic patterns are derived from task graph models of real-world applications that are simulated in parallel to the NoC at transaction level. Combining cycle-accurate router simulation and abstract task graph simulation circumvents the limitations of most NoC simulators, which either use synthetic traffic patterns or unrealistic and fixed router models. The proposed simulator architecture is presented in detail and its suitability is shown by means of a case study.

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Section: Requirementsmentioning

confidence: 99%