Survey on Real-Time Network-on-Chip Architectures

Hesham, Salma; Rettkowski, Jens; Göhringer, Diana; Ghany, Mohamed A. Abd El

doi:10.1007/978-3-319-16214-0_16

Cited by 14 publications

(10 citation statements)

References 33 publications

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“…However, such a solution does not provide by itself support to detect deadlocks, livelocks, lost message detection and the like. With respect to NoCs, the survey [156] provides a summary and quantitative comparisons (e.g., bandwidth) of relevant contributions for reliability and fault-tolerance in real-time NoCs.…”

Section: Shared Bus and Interconnection Networkmentioning

confidence: 99%

“…A SCL can be used to provide a high DC of all possible communication errors that can occur in a 'black channel', the interconnect or switch. With respect to NoCs, the survey [156] provides a summary of relevant contributions for fault detection in real-time NoCs.…”

Section: Shared Bus and Interconnection Networkmentioning

confidence: 99%

“…On the other hand, as explained in the survey [120], a relevant research activity targets the development of real-time and time predictable NoC solutions for which a generic survey and quantitative comparison is provided by [120,156]. With respect to NoC communication traffic temporal predictability, two major technical approaches can be defined: full and virtual traffic separation.…”

Section: Shared Bus and Interconnection Networkmentioning

confidence: 99%

See 2 more Smart Citations

Multi-core Devices for Safety-critical Systems

et al. 2020

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Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Section: Shared Bus and Interconnection Networkmentioning

confidence: 99%

Section: Shared Bus and Interconnection Networkmentioning

confidence: 99%

Section: Shared Bus and Interconnection Networkmentioning

confidence: 99%

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Multi-core Devices for Safety-critical Systems

et al. 2020

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“…Network-on-Chip (NoC) architecture [1,2,3,4,5,6,7,15,17] resolves the problems in un-synchronized communications, errors in signal integrity and non-scalable wire delays. By the adoption of packet switched communication architecture the two problems reusability and scalability faced by SoC designers are well addressed.…”

Section: Introductionmentioning

confidence: 99%

Design Environment for Verilog Module Analysis using Open Source Tools

2019

IJITEE

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Network-on-Chip provides possible solutions for the limitations and challenges by the present day architectures for the interconnections. The characteristics of NoCs include energy efficiency, reliability, scalability, reusability and distributed routing decisions. The existence of today’s semiconductor industry depends on shorter time-to-market, challenge of meeting increasing transistor density, reduced product life cycle, and operating frequencies getting higher. This paper discusses about a design environment for the analysis of Verilog NoC module. Tools such as Icarus Verilog, GTK Wave, Yosys etc. which are used for compilation, simulation and synthesis of the NoC are also discussed in this paper.

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“…The demand on real-time NoCs is strongly increasing since the real-time applications make out a significant portion of the embedded field, which cannot be overlooked [3]. These applications enforce timing constraints calling for guaranteed services (GS).…”

Section: Introductionmentioning

confidence: 99%

Online bicast allocation algorithm for contention-free-routing NoCs

Ahmed

Hesham

Ghany

et al. 2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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The demand on network-on-chips (NoCs) with quality of service guarantees for real-time applications has been massively increasing in the last few years. One of the main techniques used for providing such networks is timedivision-multiplexing (TDM) since it provides hard bandwidth and latency guarantees along with better resources utilization. In this paper, a runtime bicast algorithm is proposed for allocating the TDM slots in a contention-free-routing NoC. The proposed algorithm is evolved from a state-of-the art TDM allocation algorithm for point-to-point connections. The bicast algorithm shows merit in time-to-bandwidth efficiency for 80.12% of the total possible bicast connections with an average improvement of 37.76% compared with the unicast algorithm.

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Survey on Real-Time Network-on-Chip Architectures

Cited by 14 publications

References 33 publications

Multi-core Devices for Safety-critical Systems

Multi-core Devices for Safety-critical Systems

Design Environment for Verilog Module Analysis using Open Source Tools

Online bicast allocation algorithm for contention-free-routing NoCs

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