Prevention of plasma induced damage on thin gate oxide of HDP oxide deposition, metal etch, Ar preclean processing in BEOL sub-half micron CMOS processing

Wide range detector of plasma induced charging effect for advanced CMOS BEOL processes

“…[9]. In state-of-art manufacturing processes of FinFETs, numerous RF plasma steps such as etching, deposition and cleaning processes are inevitable, which create higher frequencies of plasma induced charging events [10]. Both positive and negative charging on metal structures may occur.…”

Wide Range Detector of Plasma Induced Charging Effect for Advanced CMOS BEOL Processes

“…This change not only make the devices become more susceptible to the plasma induced damage, but also might lead to unforeseen latent damages to the high-k dielectric layers [9]. In state-of-art manufacturing processes of FinFETs, numerous RF plasma steps such as etching, deposition and cleaning processes are inevitable, which create higher frequencies of plasma induced charging events [10]. Both positive and negative charging on metal structures may occur.…”

A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology

“…PID is well known to degrade both gate dielectric and metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability [2]. The silicon wafer manufacturing employs many plasma-processing steps, including gate electrode etching [3], high density plasma chemical vapor deposition (HDP-CVD) [4], metal interconnect etching [5], and photoresist ashing [6]. During plasma processing, charges (i.e., ions or electrons) accumulated from a large interconnect area cause a local imbalance in the surface potential across the gate dielectric, and cause current to flow through the gate electrode.…”