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2004
DOI: 10.1088/0960-1317/15/2/016
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Prevention method of a notching caused by surface charging in silicon reactive ion etching

Abstract: This paper proposes a method to prevent silicon from a notching in a reactive ion etching (RIE) process by introducing a self-aligned metal interlayer to a silicon/glass bonded fixture. A metal interlayer prevents a charge buildup at the bottom of a silicon trench, therefore silicon structures do not suffer from charge-induced local damage. A self-aligning process of Ti/Au interlayer is accomplished by a lift-off process using a photoresist etch mask as a sacrificial layer. Titanium is a diffusion barrier of g… Show more

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Cited by 35 publications
(22 citation statements)
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“…However, when a dielectric substrate layer such as a glass wafer is used, the notching phenomenon occurs at the interface between two layers, causing structural imperfections [16,17]. To realize the precise structures of the proposed VRG, a fabrication process was developed to prevent the notching effect using an SOPG (silicon-on-aluminum patterned glass) wafer.…”
Section: Fabricationmentioning
confidence: 99%
See 1 more Smart Citation
“…However, when a dielectric substrate layer such as a glass wafer is used, the notching phenomenon occurs at the interface between two layers, causing structural imperfections [16,17]. To realize the precise structures of the proposed VRG, a fabrication process was developed to prevent the notching effect using an SOPG (silicon-on-aluminum patterned glass) wafer.…”
Section: Fabricationmentioning
confidence: 99%
“…Post-shock measurement Tactical-grade requirement [6] Resonant frequency (kHz) 16.93 -Q-factor 61,113 -Scale factor accuracy (ppm) 49 10 to 1000 Bias instability (°/h) 0.83 0.1 to 10 Angular random walk (°/h 1/2 ) 0.083 0.5 to 0.05…”
Section: Parametersmentioning
confidence: 99%
“…The results are shown in Figure 2. While Kim described a method to prevent silicon from notching by introducing self-aligned metal interlayer to prevent charge buildup [10]. It also shows that copper is plated on the side wall uniformly and even plated at the bottom.…”
Section: Failure Analysismentioning
confidence: 99%
“…The dependencies of pressure and different slurry dilution ratios on silicon removal rate are also explored to solve the surface damages that are induced by breakthrough and stress concentration. Numerous factors affect the DRIE experimental results [ 14 , 15 , 16 ]. Thus, the main parameters including the flowrate of SF6, C4F8, oxygen, coil power, and platen power are adjusted to reduce the lag effect.…”
Section: Introductionmentioning
confidence: 99%