Abstract:This paper proposes a method to prevent silicon from a notching in a reactive ion etching (RIE) process by introducing a self-aligned metal interlayer to a silicon/glass bonded fixture. A metal interlayer prevents a charge buildup at the bottom of a silicon trench, therefore silicon structures do not suffer from charge-induced local damage. A self-aligning process of Ti/Au interlayer is accomplished by a lift-off process using a photoresist etch mask as a sacrificial layer. Titanium is a diffusion barrier of g… Show more
“…However, when a dielectric substrate layer such as a glass wafer is used, the notching phenomenon occurs at the interface between two layers, causing structural imperfections [16,17]. To realize the precise structures of the proposed VRG, a fabrication process was developed to prevent the notching effect using an SOPG (silicon-on-aluminum patterned glass) wafer.…”
Section: Fabricationmentioning
confidence: 99%
“…Post-shock measurement Tactical-grade requirement [6] Resonant frequency (kHz) 16.93 -Q-factor 61,113 -Scale factor accuracy (ppm) 49 10 to 1000 Bias instability (°/h) 0.83 0.1 to 10 Angular random walk (°/h 1/2 ) 0.083 0.5 to 0.05…”
“…However, when a dielectric substrate layer such as a glass wafer is used, the notching phenomenon occurs at the interface between two layers, causing structural imperfections [16,17]. To realize the precise structures of the proposed VRG, a fabrication process was developed to prevent the notching effect using an SOPG (silicon-on-aluminum patterned glass) wafer.…”
Section: Fabricationmentioning
confidence: 99%
“…Post-shock measurement Tactical-grade requirement [6] Resonant frequency (kHz) 16.93 -Q-factor 61,113 -Scale factor accuracy (ppm) 49 10 to 1000 Bias instability (°/h) 0.83 0.1 to 10 Angular random walk (°/h 1/2 ) 0.083 0.5 to 0.05…”
“…The results are shown in Figure 2. While Kim described a method to prevent silicon from notching by introducing self-aligned metal interlayer to prevent charge buildup [10]. It also shows that copper is plated on the side wall uniformly and even plated at the bottom.…”
Through silicon vias (TSV) is one of the key enabling technologies for 3D wafer level packaging (WLP). This paper investigates the failure causes of TSVs in a "via last" approach and presents process improvement for implementing the TSV. There are many parameter including silicon etch uniformity, dielectric etching at the bottom of the TSV, non-uniform plating and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. A new via shape that is a combination of sloped and straight etching sequence is developed in order to improve silicon dry etch effects. An improved and characterized, notch free uniform silicon etching across the wafer process based on three step etching is presented. An integration flow implementing the optimized parameters with showing electrical interconnection is given in the paper.
“…The dependencies of pressure and different slurry dilution ratios on silicon removal rate are also explored to solve the surface damages that are induced by breakthrough and stress concentration. Numerous factors affect the DRIE experimental results [ 14 , 15 , 16 ]. Thus, the main parameters including the flowrate of SF6, C4F8, oxygen, coil power, and platen power are adjusted to reduce the lag effect.…”
MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.
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