Prefetch-based dynamic row buffer management for LPDDR2-NVM devices

Abstract

LPDDR2-NVM has been announced as an industry standard to efficiently interface with non-volatile memory devices such as phase change memory (PCM). This standard interface has been adopted in most commercial PCM devices. In this paper, we devise a prefetch-based dynamic row buffer management that targets the LPDDR2-NVM devices for enhancing performance with almost negligible implementation overhead. Our extensive simulations with timing parameters from the industry's commercial PCM devices demonstrate that the proposed method enhances the performance of memory systems up to 11.3% when compared with the static optimum configuration with fairly lowcost overheads.