Unlike liquid crystal display (LCD) panels that require highintensity backlight, organic LED (OLED) display panels naturally consume low power and provide high image quality thanks to their self-illuminating characteristic. In spite of this fact, the OLED display panel is still the dominant power consumer in battery-operated devices. As a result, there have been many attempts to reduce the OLED power consumption. Since power consumption of any pixel of the OLED display depends on the color that it displays, previous power saving methods change the pixel color subject to a tolerance level on the color distortion specified by the users. In practice, the OLED power saving techniques cannot be used on common user applications such as photo viewers and movie players.This paper introduces the first OLED power saving technique that does not result in a significant degradation in the color and luminance values of the displayed image. The proposed technique is based on dynamic (driving) voltage scaling (DVS) of the OLED panel. Although the proposed DVS technique may degrade luminance of the panel, the panel luminance can be restored with appropriate image compensation. Consequently, power is saved on the OLED display panel with only minor changes in the color and luminance of the image. This technique is similar to dynamic backlight scaling of LCDs, but is based on the unique characteristics of the OLED drivers. The proposed method saves wasted power in the driver transistor and the internal resistance with an amplitude modulation driver, and in the internal resistance with a pulse width modulation driver, respectively. Experimental results show that the proposed OLED DVS with image compensation technique saves up to 52.5% of the OLED power while keeping the same human-perceived image quality for the Lena image.
Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy gain, by misleading the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We introduce new major contributors to the DVS overhead including the performance underdrive loss of the DVS-enabled microprocessor, additional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC-DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.
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