Prefetch-Aware DRAM Controllers

Lee, Chang Joo; Mutlu, Onur; Narasiman, Veynu; Patt, Yale N.

doi:10.1109/micro.2008.4771791

Cited by 143 publications

(121 citation statements)

References 29 publications

(64 reference statements)

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“…Neither of these consider fairness or system throughput in the presence of competing threads. Lee et al [6] describe a mechanism to adaptively prioritize between prefetch and demand requests in a memory scheduler; their mechanism can be combined with ours.…”

Section: Related Work: Comparison With Other Memory Schedulersmentioning

confidence: 99%

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

Kim

Papamichael

Mutlu

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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361

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In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention by arbitrating memory access in such a way that competing threads progress at a relatively fast and even pace, resulting in high system throughput and fairness. Previously proposed memory scheduling algorithms are predominantly optimized for only one of these objectives: no scheduling algorithm provides the best system throughput and best fairness at the same time.This paper presents a new memory scheduling algorithm that addresses system throughput and fairness separately with the goal of achieving the best of both. The main idea is to divide threads into two separate clusters and employ different memory request scheduling policies in each cluster. Our proposal, Thread Cluster Memory scheduling (TCM), dynamically groups threads with similar memory access behavior into either the latency-sensitive (memory-non-intensive) or the bandwidth-sensitive (memory-intensive) cluster. TCM introduces three major ideas for prioritization: 1) we prioritize the latency-sensitive cluster over the bandwidth-sensitive cluster to improve system throughput; 2) we introduce a "niceness" metric that captures a thread's propensity to interfere with other threads; 3) we use niceness to periodically shuffle the priority order of the threads in the bandwidth-sensitive cluster to provide fair access to each thread in a way that reduces inter-thread interference. On the one hand, prioritizing memory-non-intensive threads significantly improves system throughput without degrading fairness, because such "light" threads only use a small fraction of the total available memory bandwidth. On the other hand, shuffling the priority order of memory-intensive threads improves fairness because it ensures no thread is disproportionately slowed down or starved.We evaluate TCM on a wide variety of multiprogrammed workloads and compare its performance to four previously proposed scheduling algorithms, finding that TCM achieves both the best system throughput and fairness. Averaged over 96 workloads on a 24-core system with 4 memory channels, TCM improves system throughput and reduces maximum slowdown by 4.6%/38.6% compared to ATLAS (previous work providing the best system throughput) and 7.6%/4.6% compared to PAR-BS (previous work providing the best fairness).

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Section: Related Work: Comparison With Other Memory Schedulersmentioning

confidence: 99%

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

Kim

Papamichael

Mutlu

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

Self Cite

361

377

View full text Add to dashboard Cite

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“…It also utilizes a memory scheduler to decide which memory request should be scheduled next. A large body of previous work developed various memory scheduling policies [4,23,24,34,41,42,48,49,61,62,63,64,65,67,76,77,84,85,95]. Traditional commodity systems employ a variant of the first-ready first-come-first-serve (FR-FCFS) scheduling policy [76,77,95], which prioritizes memory requests that are row-buffer hits over others and, after that, older memory requests over others.…”

Section: Conventional Memory Scheduling Mechanismsmentioning

confidence: 99%

“…To evaluate fairness, we consider both the individual slowdown of each application [48] and the maximum slowdown [17,41,42,87] across both applications in a workload. We make several major observations.…”

Section: Analysis Of Prior and Naïve Scheduling Policiesmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Byte-addressable nonvolatile memories promise a new technology, persistent memory, which incorporates desirable attributes from both traditional main memory (byte-addressability and fast interface) and traditional storage (data persistence). To support data persistence, a persistent memory system requires sophisticated data duplication and ordering control for write requests. As a result, applications that manipulate persistent memory (persistent applications) have very different memory access characteristics than traditional (non-persistent) applications, as shown in this paper. Persistent applications introduce heavy write traffic to contiguous memory regions at a memory channel, which cannot concurrently service read and write requests, leading to memory bandwidth underutilization due to low bank-level parallelism, frequent write queue drains, and frequent bus turnarounds between reads and writes. These characteristics undermine the high-performance and fairness offered by conventional memory scheduling schemes designed for non-persistent applications.Our goal in this paper is to design a fair and high-performance memory control scheme for a persistent memory based system that runs both persistent and non-persistent applications. Our proposal, FIRM, consists of three key ideas. First, FIRM categorizes request sources as non-intensive, streaming, random and persistent, and forms batches of requests for each source. Second, FIRM strides persistent memory updates across multiple banks, thereby improving bank-level parallelism and hence memory bandwidth utilization of persistent memory accesses. Third, FIRM schedules read and write request batches from different sources in a manner that minimizes bus turnarounds and write queue drains. Our detailed evaluations show that, compared to five previous memory scheduler designs, FIRM provides significantly higher system performance and fairness.

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“…al. [18] propose using prefetch accuracy information to determine whether to prioritize demands over prefetches or to treat them equally in terms of memory scheduling. To our knowledge, this is the only prior work that deals with how prefetches should be dealt with in a shared resource.…”

Section: Prefetch-aware Dram Controllersmentioning

confidence: 99%

Prefetch-aware shared resource management for multi-core systems

Ebrahimi

Lee

Mutlu

et al. 2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

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100

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Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these shared resources; however, none of them take into account prefetch requests. Without prefetching, significant performance is lost, which is why existing systems prefetch. By not taking into account prefetch requests, recent shared-resource management proposals often significantly degrade both performance and fairness, rather than improve them in the presence of prefetching.This paper is the first to propose mechanisms that both manage the shared resources of a multi-core chip to obtain highperformance and fairness, and also exploit prefetching. We apply our proposed mechanisms to two resource-based management techniques for memory scheduling and one source-throttling-based management technique for the entire shared memory system. We show that our mechanisms improve the performance of a 4-core system that uses network fair queuing, parallelism-aware batch scheduling, and fairness via source throttling by 11.0%, 10.9%, and 11.3% respectively, while also significantly improving fairness.

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Prefetch-Aware DRAM Controllers

Cited by 143 publications

References 29 publications

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Prefetch-aware shared resource management for multi-core systems

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