Prefetch-aware shared resource management for multi-core systems

Abstract

Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these shared resources; however, none of them take into account prefetch requests. Without prefetching, significant performance is lost, which is why existing systems prefetch. By not taking into account prefetch requests, recent shared-resource management proposals often significantly degrade both performance and fairness, rather than improve them in the presence of prefetching.This paper is the first to propose mechanisms that both manage the shared resources of a multi-core chip to obtain highperformance and fairness, and also exploit prefetching. We apply our proposed mechanisms to two resource-based management techniques for memory scheduling and one source-throttling-based management technique for the entire shared memory system. We show that our mechanisms improve the performance of a 4-core system that uses network fair queuing, parallelism-aware batch scheduling, and fairness via source throttling by 11.0%, 10.9%, and 11.3% respectively, while also significantly improving fairness.

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

“…It also utilizes a memory scheduler to decide which memory request should be scheduled next. A large body of previous work developed various memory scheduling policies [4,23,24,34,41,42,48,49,61,62,63,64,65,67,76,77,84,85,95]. Traditional commodity systems employ a variant of the first-ready first-come-first-serve (FR-FCFS) scheduling policy [76,77,95], which prioritizes memory requests that are row-buffer hits over others and, after that, older memory requests over others.…”

“…Prior memory controllers (e.g., [23,24,41,42,49,63,64,65,76,77,95]) buffer writes in a write queue to allow read requests to aggressively utilize the memory bus. When the write queue is full or is filled to a predefined level, the memory scheduler switches to a write drain mode where it drains the write queue either fully or to a predetermined level [49,78,83], in order to prevent stalling the entire processor pipeline.…”

“…FIRM does this in a manner that balances the amount of time spent in write drain mode (servicing write batches) and read mode (servicing read batches) in a way that is proportional to the read and write demands, while ensuring that time spent in each mode is long enough such that the wasted cycles due to bus turnaround delays are minimized. When the memory scheduler is servicing read or persistent write batches, in read mode or write drain mode, the scheduling policy employed can be any of the previously-proposed memory request scheduling policies (e.g., [23,41,42,49,64,65,76,77,95]) and the ordering of persistent write batches is fixed by the ordering control of persistent applications. The key novelty of our proposal is not the particular prioritization policy between requests, but the mechanism that determines how to group batches and when to switch between write drain mode and read mode, which we describe in detail next.…”

AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance

“…Several works in recent years have proposed novel hardware prefetching schemes for improving the utilization of shared resources (offchip bandwidth and LLC capacity) in multicores [2,3,4,7,17,22]. Liu and Solihin [12] have proposed analytical models for bandwidth partitioning to identify when prefetching can help in improving system performance.…”

Exploiting the Role of Hardware Prefetchers in Multicore Processors

“…They have proposed mechanisms to maximize DRAM Bank Level Parallelism (BLP) using BLP-aware Prefetch Issue (BAPI) with BLP-Preserving Multi core Request Issue (BPMRI) that helps improve the application performance with parallel servicing of requests. Ebrahimi et al [20] have proposed mechanisms to exploit prefetching for shared resource management in multicore systems.…”