Prediction of thermo-mechanical integrity of wafer backend processes

Gonda, Viktor; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; Driel, W.D. van; Hoofman, R.J.O.M.; Ernst, L.J.

doi:10.1016/j.microrel.2004.05.021

Cited by 17 publications

(7 citation statements)

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“…[15][16][17][18] Especially, electrolessly deposited Cu films, intensively studied as a potential Cu metallization in finely patterned features below 90 nm, [10][11][12][13][14] are reported to possess ultrafine grains sizes Ͻ10 nm. 13,14 The nanocrystalline structure of electroless Cu films is expected to further alter mechanical properties since the plastic deformation is no longer based on dislocation activity, but rather by grainboundary sliding as the inverse Hall-Petch effect.…”

Section: Introductionmentioning

confidence: 99%

“…To further avoid failure, the architecture of interconnect structures can be modified to redistribute stresses in the structures through the realization of the initiation of permanent plastic deformation of Cu films. 15,16 An instrumented nanoindentation test has been widely utilized for measuring the hardness and elastic modulus of materials. 19,20 In addition to basic experimental data such as that for hardness and elastic modulus, true mechanical responses, including stress criteria and the onset of plasticity ͑dislocation burst phenomenon͒, have been also examined.…”

Section: Introductionmentioning

confidence: 99%

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Grain size effect on nanomechanical properties and deformation behavior of copper under nanoindentation test

Chang

2007

Journal of Applied Physics

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The mechanical properties and deformation behaviors of copper with different grain sizes have been investigated in this study by instrumented nanoindentation. Following the Hall-Petch relation, the hardness of copper specimens increased as the grain size decreased. Dislocations were clearly observed in deformed regions around indent marks, indicating plastic deformation by dislocation formation and sliding. However, the hardness of electroless copper films with an ultrafine grain size of only 10 nm dropped. Voiding at grain boundaries and triple grain junctions was observed as a consequence of grain-boundary sliding and grain rotation, which was expected as the dominant deformation mechanism resulting in the reduced hardness. The critical shear stresses for the initiation of plastic deformation in the copper specimens with large grain sizes were close to the theoretical value and comparatively much lower for electroless copper films with an ultrafine grain size. (c) 2007 American Institute of Physics

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Grain size effect on nanomechanical properties and deformation behavior of copper under nanoindentation test

Chang

2007

Journal of Applied Physics

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“…FE techniques are widely used to predict the deformations and stresses and their evolution during IC processes, packaging manufacturing processes, and/or product testing [4,5,8,[17][18][19][20][21][22][23][24][25][26]. Modelling techniques such as contact elements, global-local, sub-structuring, element birth and death, fracture mechanics and material models such as visco-elasticity, plasticity and creep are rapidly developed to predict the stress and strain state in the electronic Fig.…”

Section: Facing the Future: Cmos065 And Beyondmentioning

confidence: 99%

“…Moreover, the use of copper requires a dedicated processing technique, which is called the damascene process. But the most important change is that the adhesion between low-k and the adjacent materials is very poor [5][6][7]. Fig.…”

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confidence: 99%

Facing the challenge of designing for Cu/low-k reliability

Driel

2007

Microelectronics Reliability

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“…Therefore, it is urgent and practical to use finite element analysis (FEA) method to do more parametric studies to understand and reduce TSV wafer warpage and stress. FEA method has been widely used in the thermo-mechanical reliability analysis of 3D IC package with TSV in different levels, such as via level [9][10], stack via level [11][12][13], and package level [14][15]. However, it is lack of wafer level modeling and simulation for TSV wafer.…”

Section: Introductionmentioning

confidence: 99%

Wafer level warpage modeling methodology and characterization of TSV wafers

Zhang

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment data. With using the developed model, wafer warpage has been simulated and analyzed by considering different factors such as annealing temperature, Cu overburden thickness, TSV depth and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and increasing Cu overburden thickness. Such findings have been successfully used in the TSV process optimization to reduce wafer warpage after annealing process. Submodeling methodology has also been developed to determine wafer stress accurately. Wafer bending stress is larger at wafer surface and close to the TSV edge. Bending stress is higher at the edge of TSV with finer pitch.

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Prediction of thermo-mechanical integrity of wafer backend processes

Cited by 17 publications

References 1 publication

Grain size effect on nanomechanical properties and deformation behavior of copper under nanoindentation test

Grain size effect on nanomechanical properties and deformation behavior of copper under nanoindentation test

Facing the challenge of designing for Cu/low-k reliability

Wafer level warpage modeling methodology and characterization of TSV wafers

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