Pre-layout estimation of individual wire lengths

Bodapati, Srinivas; Najm, Farid N.

doi:10.1145/333032.333038

Cited by 32 publications

(23 citation statements)

References 4 publications

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“…To gauge the inherent noise in capacitance estimation, we take an approach similar to that used in [25]. Specifically, we place each benchmark circuit (using Xilinx tools) and generate a placed netlist.…”

Section: B Noise In Interconnect Capacitancementioning

confidence: 99%

Power estimation techniques for FPGAs

Anderson

Najm

2004

IEEE Trans. VLSI Syst.

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Abstract-The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.

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Section: B Noise In Interconnect Capacitancementioning

confidence: 99%

Power estimation techniques for FPGAs

Anderson

Najm

2004

IEEE Trans. VLSI Syst.

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“…This approach can make predictions only on intra-cluster nets, which tend to be short in the final placement. Another solution is proposed by Bodapati and Najm [1]. Their method requires building black-box models for the place-and-route tools, which is a timeconsuming task.…”

Section: 3mentioning

confidence: 99%

Pre-layout wire length and congestion estimation

Liu

Marek-Sadowska

2004

Proceedings of the 41st Annual Design Automation Conference

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In this paper, we study the pre-layout wire length and congestion estimation. We find that two structural metrics, mutual contraction and net range, can be used to predict wire lengths. These metrics have different application ranges and complement each other. We also propose a new metric, the structural pin density, to capture the peak routing congestion of designs. Larger maximum pin densities usually lead to larger peak congestions in circuits with similar average congestions. We demonstrate experimentally very good correlation of our pre-layout measures with post layout interconnect lengths. We also isolate the structural netlist properties which cause the peak congestion.

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“…There are a number of methods for predicting wire length before placement and routing have taken place [2,3,4]. Most of these methods apply to ASIC CAD flows.…”

Section: Introductionmentioning

confidence: 99%

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

Manohararajah

Chiu

Singh

et al. 2007

IEEE Trans. VLSI Syst.

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This paper studies the prediction of interconnect delay in an industrial setting. Industrial circuits and two industrial FPGA architectures were used in the study. We show that there is a large amount of inherent randomness in a state-ofthe-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Futhermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Using this simple timing model in a two-phase timing driven physical synthesis flow can both improve quality of results and decrease runtime. Next, we present a metric for predicting the accuracy of our interconnect delay model and show how this metric can be used to reduce the runtime of a timing driven physical synthesis flow. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction.

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Pre-layout estimation of individual wire lengths

Cited by 32 publications

References 4 publications

Power estimation techniques for FPGAs

Power estimation techniques for FPGAs

Pre-layout wire length and congestion estimation

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

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