Pre-layout delay calculation specification for CMOS ASIC libraries

Edamatsu, H.; Homma, K.; Kakimoto, M.; Koike, Y.; Tabuchi, K.

doi:10.1109/aspdac.1998.669457

Cited by 10 publications

(4 citation statements)

References 6 publications

(2 reference statements)

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“…The interconnect delay is also modeled as a random variable and is pre-characterized once the RCs are extracted. Next, the random variable of the signal arrival time at any cell/interconnect output can be computed using the information on the arrival and transition times of the cell fanins as well as the information on the cell/interconnect delay [5].…”

Section: Statistical Timing Analysismentioning

confidence: 99%

Performance sensitivity analysis using statistical method and its applications to delay

Liou

Krstić

Cheng

et al. 2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. We propose a statistical framework for analyzing the performance sensitivity of designs to various timing related defects/noise/variations. The core engine of our approach is a highly efficient statistical timing analysis tool. We describe the application of our framework for delay fault modeling and analysis of resistive opens and shorts and as well as interconnect crosstalk. We present experimental results demonstrating the accuracy of our statistical framework as compared to SPICE (for a given set of input patterns) and nominal worst-case analysis. Experimental results for analysis of resistive opens and shorts are also included.

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Section: Statistical Timing Analysismentioning

confidence: 99%

Performance sensitivity analysis using statistical method and its applications to delay

Liou

Krstić

Cheng

et al. 2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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“…To reflect the electrical masking effect of transient faults on one cell intertwined with process variations, an approach similar to Edamatsu et al [1998] is employed to extract precharacterized tables. The objective of such precharacterized tables is to model the pulse width and voltage magnitude for each cell as random variables that can be sampled during the particle-strike process and transient-fault propagation of one cell.…”

Section: Cell Precharacterizationmentioning

confidence: 99%

Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

Peng

Huang

Kuo

et al. 2012

ACM Trans. Des. Autom. Electron. Syst.

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This article re-examines the soft error effect caused by radiation-induced particles beyond the deep submicron regime. Considering the impact of process variations, voltage pulse widths of transient faults are found no longer monotonically diminishing after propagation, as they were formerly. As a result, the soft error rates in scaled electronic designs escape traditional static analysis and are seriously underestimated. In this article we formulate the statistical soft error rate (SSER) problem and present two frameworks to cope with the aforementioned sophisticated issues. The table-lookup framework captures the change of transient-fault distributions implicitly by using a Monte-Carlo approach, whereas the SVR-learning framework does the task explicitly by using statistical learning theory. Experimental results show that both frameworks can more accurately estimate SERs than static approaches do. Meanwhile, the SVR-learning framework outperforms the table-lookup framework in both SER accuracy and runtime.

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“…The interconnect delay is also modeled as a random variable and is pre-characterized once the RCs are extracted. Next, the random variable of the signal arrival time at any cell/interconnect output can be computed using the arrival and transition times of the cell fanins and the information on the cell/interconnect delay [14].…”

Section: Statistical Timing Analysis Frameworkmentioning

confidence: 99%

Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis

Liou

Cheng²,

Mukherjee³

Proceedings 18th IEEE VLSI Test Symposium

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The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in nature. In order to capture the effects of these statistical variations on circuit performance, we incorporate statistical information in timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. We further propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure caused by the target type of defect, noise or variation source. This new path selection methodology defines a new path/segment searching paradigm for detecting delay faults in deep sub-micron devices. 0-7695-0613-5/00 $10.00 ã 2000 I

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Pre-layout delay calculation specification for CMOS ASIC libraries

Abstract: Abstract

Cited by 10 publications

References 6 publications

Performance sensitivity analysis using statistical method and its applications to delay

Performance sensitivity analysis using statistical method and its applications to delay

Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis

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