Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

Peng, Hao‐Kai; Huang, Hsuan-Ming; Kuo, Yu-Hsin; Wen, Charles H.-P.

doi:10.1145/2071356.2071365

Cited by 8 publications

(4 citation statements)

References 34 publications

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“…Moreover, the state and node dependence problem in cell characterization, along with the important waveforms refinement problem in glitch propagation were also considered in [7]. [25] employed support vector regression technique for the glitch generation and propagation calculation, but the machine learning approach has higher computing complexity and limit the analysis speed. CASSER in [11] used statistical closed-form analysis technique to examine the SER fluctuation under process variation, and reported dramatic performance improvement over reference [25].…”

Section: Related Workmentioning

confidence: 99%

Parallel SER analysis for combinational and sequential standard cell circuits

Sheng

Jiang

Mao

2016

Microelectronics Journal

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A parallel SER (soft error rate) evaluation framework ASSET-VLG was developed to analyze the SER of both combinational and sequential standard cell circuits. ASSET-VLG was constructed in practically oriented way: i) it employs a verilog parser for automatically reading the synthesized DUT (device under test) netlist; ii) it provides an accurate and unified SER analysis framework for both the combinational and sequential circuits rather than the former only; iii) it targets to a 130 nm production library and the modeling method can be easily ported to newer technologies. Furthermore, concurrency is also exploited for accelerating the evaluation procedure on modern multi-core computers. These features make ASSET-VLG appropriate for automatic SER estimation in design stage and can be easily integrated into current highly reliable ICs design flow. Experiments on ISCAS'85 and IS-CAS'89 benchmark circuits show the evaluation time ranges from 0.5 ms to 2.16 s without previous memory explosion problem. Compared with spice, the modeling method of ASSET-VLG provides 98% accuracy. The parallelizing experiments indicate the proposed method has better scalability, e.g., 4.44 X speedup are obtained in a 4 cores/8 threads platform. The experiments also reveal that sequential part (flip-flops) in the circuit dominating the system SER by one order than combinational gates for a 130 nm CMOS $ process. Last but not least, significant frequency dependence of SER are observed in flip-flops, implying the commonly used critical charge measure is insufficient for characterizing soft error in sequential cells.

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Section: Related Workmentioning

confidence: 99%

Parallel SER analysis for combinational and sequential standard cell circuits

Sheng

Jiang

Mao

2016

Microelectronics Journal

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“…Reference Miskov-Zivanov et al (2008) presents a linear approximation between gates delay and process variation parameters. Authors in (Peng et al, 2009(Peng et al, , 2012 assume that the transient pulse width has a normal distribution with known parameters. Recently, CASEER (Chang et al 2013).…”

Section: Introductionmentioning

confidence: 99%

Statistical soft error rate estimation of combinational circuits using Bayesian networks

Sabet

Ghavami

2016

COMPEL

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Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation. Design/methodology/approach In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated. Findings Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime. Originality/value The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.

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“…The soft errors are caused when the state of a digital circuit is changed due to accumulation of extra charge in the circuit primarily because of the strike of a sub-atomic particles on the circuit. The scaling of technology has increased the probability of soft error due to decrease in "critical charge" required to change the state of a digital circuit (e.g., [2], [3]). Therefore, both hard and soft errors should be considered while evaluating the reliability of the system.…”

mentioning

confidence: 99%

Reliable system design using decision diagrams in presence of hard and soft errors

Israr

Huss

2014

Proceedings of 2014 11th International Bhurban Conference on Applied Sciences &Amp; Technology (IBCAST) Islamabad, Pakistan, 14

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Hard and soft errors are inherently different in property and effect on the functionality of systems. Utilizing this fact, a new reliability model is developed, i.e., "lifetime reliability", which considers both hard and soft errors occurring in information processing systems.Based on an introduction of System Decision Diagrams a couple of new data structures denoted as System Resource Decision Diagram and System Task Instance Decision Diagram, respectively, are proposed. The first data structure deals with the hard errors occurring in the system, whereas the second one represents the effects soft errors have on the system's functionality. Together, these data structures help calculate the lifetime reliability of the system they are representing. Both the construction of this diagram pair and the memory-aware evaluation of the reliability based on it are detailed in an algorithmic way. The error model representation and the reliability quantification approach are aimed to be employed in a high-level design process to accelerate exploration of design space.The proposed method is illustrated for a number of benchmarks taken from published papers. The achieved results demonstrate that this novel approach is highly memory efficient and at the same time accurate as compared to previous known schemes. Index Terms-SystemDecision Diagrams, zero-suppressed decision diagram, hard error, soft error, system-level design, embedded system, reliability evaluation

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Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

Cited by 8 publications

References 34 publications

Parallel SER analysis for combinational and sequential standard cell circuits

Parallel SER analysis for combinational and sequential standard cell circuits

Statistical soft error rate estimation of combinational circuits using Bayesian networks

Reliable system design using decision diagrams in presence of hard and soft errors

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