Parallel SER analysis for combinational and sequential standard cell circuits

Abstract

A parallel SER (soft error rate) evaluation framework ASSET-VLG was developed to analyze the SER of both combinational and sequential standard cell circuits. ASSET-VLG was constructed in practically oriented way: i) it employs a verilog parser for automatically reading the synthesized DUT (device under test) netlist; ii) it provides an accurate and unified SER analysis framework for both the combinational and sequential circuits rather than the former only; iii) it targets to a 130 nm production library and the modeling method can be easily ported to newer technologies. Furthermore, concurrency is also exploited for accelerating the evaluation procedure on modern multi-core computers. These features make ASSET-VLG appropriate for automatic SER estimation in design stage and can be easily integrated into current highly reliable ICs design flow. Experiments on ISCAS'85 and IS-CAS'89 benchmark circuits show the evaluation time ranges from 0.5 ms to 2.16 s without previous memory explosion problem. Compared with spice, the modeling method of ASSET-VLG provides 98% accuracy. The parallelizing experiments indicate the proposed method has better scalability, e.g., 4.44 X speedup are obtained in a 4 cores/8 threads platform. The experiments also reveal that sequential part (flip-flops) in the circuit dominating the system SER by one order than combinational gates for a 130 nm CMOS $ process. Last but not least, significant frequency dependence of SER are observed in flip-flops, implying the commonly used critical charge measure is insufficient for characterizing soft error in sequential cells.