Practical Silicon-Surface-Protection Method using Metal Layer

Abstract

Abstract-The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical siliconsurface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

Hardware Security For and Beyond CMOS Technology

“…Countermeasures seek to prevent and/or detect the physical access. Solutions include, e.g., shielding structures in the BEOL [29][30][31], deflection or scrambling structures in the substrate [32], and detector circuitry [33]. Earlier studies such as [34] also considered formally secure techniques.…”

3D Integration: Another Dimension Toward Hardware Security

“…Semi-or fully-invasive probing, monitoring, fault injection, or even circuit modifications are arguably the most severe threats for hardware security at runtime. Related attacks and various countermeasures have been demonstrated for classical 2D ICs, e.g., see [32], [33], [34] and [35], [36], [37], [38].…”