Practical Monte-Carlo based timing yield estimation of digital circuits

Jaffari,; Anis,

doi:10.1109/date.2010.5456941

Cited by 4 publications

(3 citation statements)

References 12 publications

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“…7, the designer's circuit specifications defined in Table I are considered. Contrary to the previous sections, we do not consider the order statisticsbase control variates method [7] in these graphs as the authors advise against using it in [1] for high yield estimation with a moderate sample size.…”

Section: A Test Circuitsmentioning

confidence: 80%

“…Then the yield estimate is obtained from the theoretical cumulative distribution function of the parametric distribution. For example, a skew-normal distribution combined with the control variates method is used in [1], a shifted-gamma distribution combined with a low discrepancy sequence in [2] and a shifted log-normal distribution combined with a modified Latin Hypercube sampling in [3]. The yield estimate based on a parametric distribution usually converges faster than nonparametric estimates.…”

Section: Introductionmentioning

confidence: 99%

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An efficient control variates method for yield estimation of analog circuits based on a local model

Desrumaux

Dupret

Tingleff

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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Statistical analysis of analog circuits usually relies on the standard Monte Carlo method to estimate the yield of a circuit. However, this method is limited by a slow convergence rate which leads to a prohibitive number of simulations to reach a given accuracy. In this paper, we propose to combine the kernelbased distribution estimator with the control variates method in order to obtain an accurate yield estimation with only a few hundred simulations. With respect to the auxiliary variable needed for the control variates method, we propose a quick modeling technique based on local sensitivities.

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Section: A Test Circuitsmentioning

confidence: 80%

Section: Introductionmentioning

confidence: 99%

An efficient control variates method for yield estimation of analog circuits based on a local model

Desrumaux

Dupret

Tingleff

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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show abstract

“…Therefore, it is natural to determine the timing yield of a circuit using the statistical methods. Another work which evaluated timing yield by using Monte Carlo approach is by Javid Jaffri [13]. This work explores the sampling based approach for calculating the timing yield of a circuit.…”

Section: Timing Yieldmentioning

confidence: 99%

Timing Verification for Adaptive Integrated Circuits

Kumar¹,

Li²,

Shen³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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An adaptive circuit can perform built-in self-detection of timing variations and accordingly adjust itself to avoid timing violations. Compared with conventional over-design approach, adaptive circuit design is conceptually advantageous in terms of power-efficiency. Although the advantage has been witnessed in numerous previous works including test chips, adaptive design is far from being widely used in practice.A key reason is the lack of corresponding timing verification support. We developed new timing analysis techniques to fill this void. A main challenge is the large runtime complexity due to numerous adaptivity configurations. We propose several pruning and reduction techniques and apply them in conjunction with statistical static timing analysis (SSTA). The proposed method is validated on benchmark circuits including the recent ISPD'13 suite, which has circuit as large as 150K gates. The results show that our method can achieve orders of magnitude speed-up over Monte Carlo simulation with about the same accuracy. It is also several times faster than an exhaustive application of SSTA.

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