An efficient control variates method for yield estimation of analog circuits based on a local model

Desrumaux, Pierre-Francois; Dupret, Yoan; Tingleff, Jens; Minehane, S.; Redford, M.; Latorre, Laurent; Nouet, Pascal

doi:10.1145/2429384.2429471

Cited by 4 publications

(1 citation statement)

References 16 publications

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“…Both of them may lead to substantial yield loss at an advanced technology node. Hence, accurate yield estimation has been identified as one of the top priorities for both pre-silicon verification [3]- [5] and post-silicon validation [6]- [7] in order to improve circuit performance and/or reduce manufacturing cost.…”

Section: Introductionmentioning

confidence: 99%

BMF-Bd

Fang

Yang

Zeng

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Accurate yield estimation is one of the important yet challenging tasks for both pre-silicon verification and post-silicon validation. In this paper, we propose a novel method of Bayesian model fusion on Bernoulli distribution (BMF-BD) for efficient yield estimation at the late stage by borrowing the prior knowledge from an early stage. BMF-BD is particularly developed to handle the cases where the pre-silicon simulation and/or post-silicon measurement results are binary: either "pass" or "fail". The key idea is to model the binary simulation/measurement outcome as a Bernoulli distribution and then encode the prior knowledge as a Beta distribution based on the theory of conjugate prior. As such, the late-stage yield can be accurately estimated through Bayesian inference with very few late-stage samples. Several circuit examples demonstrate that BMF-BD achieves up to 10× cost reduction over the conventional estimator without surrendering any accuracy.

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