PPAC scaling enablement for 5nm mobile SoC technology

Metrology for the next generation of semiconductor devices

“…Integrated circuit scaling has been made possible by concurrently reducing device geometrical dimensions, increasing drive current, and reducing voltage. This is increasingly difficult to do because of the rising importance of parasitics (for example, coupling capacitance due to feature proximity) and higher manufacturing costs 9 . In addition to geometrical scaling, new device structures and designs that allow better drive current scaling 10-12 , better connections to the device and better interconnect are needed 13,14 .…”

“…The fin-based field-effect transistor (FinFET) 15 will remain the mainstream device option until 2021 when gate all around (GAA) devices would need to be introduced to provide enhanced performance at smaller dimensions due to better electrostatics control 9,16 . Lateral GAA (LGAA), which is closer to FinFETs in structure, would be implemented first, followed by vertical GAA (VGAA).…”

“…1b) because of process and electrical limits. These limits include but are not limited to: worsening resistance and time-dependent-dielectric-breakdown in the metals 17 ; worsening coupling capacitance between gate and drain 9 ; worsening short-channel behaviour due to gate length 16 ; and mobility degradation by reduced device width and mechanical stability of fins and GAA devices 11 .…”

Outlook of device and assembly technologies enabling high-performance mobile computing

“…This would provide a better solution for a lower via resistance at scaled dimensions and a better integration window to fill the narrow interconnect trenches [7]. Higher bulk resistivity of non-Cu solutions is already apparent in the power distribition and this would require selective high-aspect ratio metallization for those PDN networks [2]. In order to resolve the increasing resistance of signal routing, a hierarchical wiring approach such as scaling of line length can overcome the problem of increasing wire resistance per datapath [8].…”

“…This becomes more difficult whenever the cost of wafer processing becomes more expensive with the increased number of steps caused by multiple-patterning lithography steps. In order to compensate for the cost of complexity, acceleration in design efficiency with the use of DTCO enhanced technologies is needed to further scale down area so as to reach the die-cost scaling targets [2] In this paper we will briefly describe the scaling of these technology drivers and their evolution by scaling.…”