PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

Lichtenau, Cedric; Ringler, M.I.; Pfluger, T.; Geissler, S.; Hilgendorf, R.; Heaslip, J.; Weiss, U.; Sandon, Peter A.; Rohrer, Norman J.; Cohen, E.; Canada, M.

doi:10.1109/isscc.2004.1332741

Cited by 21 publications

(6 citation statements)

References 1 publication

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“…For the DFB scheme, only few cycles are lost during the frequency transition. IBM's PowerTune technology [Lichtenau et al 2004] generates multiple frequencies which are selected using multiplexers. The overhead to switch between frequencies was reported to be one cycle.…”

Section: Performance Overheadsmentioning

confidence: 99%

Does the Sharing of Execution Units Improve Performance/Power of Multicores?

Rodrigues

Koren

Kundu

2015

ACM Trans. Embed. Comput. Syst.

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Several studies and recent real world designs have promoted sharing of underutilized resources between cores in a multicore processor to achieve better performance/power. It has been argued that when utilization of such resources is low, sharing has negligible impact on performance, while offering considerable area and power benefits . In this paper we investigate the performance and performance/Watt implications of sharing large and underutilized resources between pairs of cores in a multicore. We first study sharing of the entire floating-point datapath (including reservation stations and execution units) by two cores, similar to AMD's Bulldozer. We find that while this architecture results in power savings, for certain workload combinations, it also results in significant performance loss of about 28%. Next, we study an alternative sharing architecture where only the floating-point execution units are shared, while the individual cores retain their reservation stations. This reduces the performance loss to 14%. We then extend the study to include sharing of other large execution units that are used infrequently, namely the integer multiply and divide units. Subsequently, we analyze the impact of sharing hardware resources in Simultaneously MultiThreaded (SMT) processors where multiple threads run concurrently on the same core. It is observed that sharing improves performance/Watt at a negligible performance cost only if the shared units have high throughput. Sharing low throughput units reduces both performance and performance/Watt. To increase the throughput of the shared units we propose the use of Dynamic Voltage and Frequency Boosting (DVFB) of only the shared units that can be placed on a separate voltage island. Our results indicate that the use of DVFB improves both performance and performance/Watt by as much as 22% and 10%, respectively.

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Section: Performance Overheadsmentioning

confidence: 99%

Does the Sharing of Execution Units Improve Performance/Power of Multicores?

Rodrigues

Koren

Kundu

2015

ACM Trans. Embed. Comput. Syst.

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“…This sequence is commonly used in modern voltage-scaled processors, including the Intel Core Duo processor architecture [11]. IBM's PowerTune technology is able to make a frequency transition in one cycle using multiple pre-generated clocks and selecting one by a multiplexor [12]. Although our proposed model focuses on conventional digital PLLs, it is applicable to this technology as well except for the PLL lock time in Section 4.3.1.…”

Section: Clock Frequency Transitionmentioning

confidence: 99%

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Park

Shin

Chang

et al. 2010

Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design

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Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy gain, by misleading the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We introduce new major contributors to the DVS overhead including the performance underdrive loss of the DVS-enabled microprocessor, additional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC-DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.

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“…The noise suppression by decreasing the package inductance and increasing the on-chip decoupling capacitance leads to the large area penalty. Conventional clock dithering 15) and power switch control 16) to slow the current change increase the wake-up time and are not useful for the frequent wake-up and power-down. To solve these problems, an on-chip noise canceller with small area penalty and the fast wake-up is proposed.…”

Section: Power Supply Noise Cancellermentioning

confidence: 99%

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

Takamiya

Sakurai

2009

IPSJ Transactions on System LSI Design Methodology

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In order to cope with the increasing leakage power and the increasing device variability in VLSI's, the required control size of both the space-domain and the time-domain is decreasing. This paper shows the several recent fine-grain voltage engineerings for the low power VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain power supply voltage with 3D-structured on-chip buck converters with the maximum power efficiency up to 71.3% in 0.35-µm CMOS and the fine-grain body bias control to reduce power supply voltage in 90-nm CMOS. The time-domain fine-grain voltage engineering includes accelerators for the power supply voltage hopping with a 5-ns transition time in 0.18-µm CMOS, the power supply noise canceller with the 32% power supply noise reduction in 90-nm CMOS, and backgate bias accelerators for fast wake-up with 1.5-V change of backgate voltage in 35 ns in 90-nm CMOS.

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PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

Cited by 21 publications

References 1 publication

Does the Sharing of Execution Units Improve Performance/Power of Multicores?

Does the Sharing of Execution Units Improve Performance/Power of Multicores?

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

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