Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP

Abstract

Power integrity design is a critical issue in system-inpackages (SiP's). In particular, power supply disturbance excited by simultaneous switching output (SSO) noise, or core circuits is serious in a 3D stacked die packages. Therefore, decoupling schemes in such SiP's must be carefully designed to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range and to avoid the parallel resonance occurred by chip-package connection. In this paper, a test chip was designed and fabricated to generate noise and to monitor on-chip power supply noise. Then, a power noise evaluation system has been established. Power supply noise on core circuits was measured with a noise monitoring circuit. The noise on output buffer circuit was measured by a fixed high/low method. Power supply noises were examined in various decoupling schemes. They are with embedded SMD capacitors inside interposer, and SMD capacitors mounted on the backside of interposer along with on-chip capacitance.